Method for producing pillar-shaped semiconductor device

ABSTRACT

The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate, a Si pillar and an impurity region located in a lower portion of the Si pillar and serving as a source or a drain, a step of forming a SiO 2  layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region in plan view, a step of forming a SiO 2  layer on the SiO 2  layer such that the SiO 2  layer surrounds the Si pillar in plan view, a step of forming a resist layer that is partly connected to the SiO 2  layer in plan view, and a step of forming a SiO 2  layer by etching the SiO 2  layer below the SiO 2  layer and the resist layer using the SiO 2  layer and the resist layer as masks.

CROSS REFERENCES TO RELATED APPLICATIONS

The present application is a continuation-in part application of U.S. patent application Ser. No. 15/976,510, filed May 10, 2018 and granted Oct. 5, 2018, which is a continuation of PCT patent application No. PCT/JP2016/085295, filed Nov. 29, 2016, which claims priority to PCT patent application No. PCT/JP2015/085469, filed Dec. 18, 2015. The contents of these applications are incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a method for producing a pillar-shaped semiconductor device.

2. Description of the Related Art

In recent years, semiconductor devices including SGTs have been required to have higher density and higher performance.

In planar MOS transistors, the channel of a P- or N-channel MOS transistor is formed in a horizontal direction along the surface of a semiconductor substrate between the source and the drain. In contrast, the channel of an SGT is formed in a direction vertical to the surface of a semiconductor substrate (e.g., refer to Japanese Unexamined Patent Application Publication No. 2-188966 and Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991)).

FIG. 15 illustrates a schematic structure of an N-channel SGT. N⁺ regions 116 a and 116 b are formed in a lower portion and an upper portion of a P-type or i-type (intrinsic) Si pillar 115 (hereafter a silicon semiconductor pillar is referred to as a “Si pillar”). When one of the N⁺ regions 116 a and 116 b functions as a source, the other functions as a drain. A portion of the Si pillar 115 between the source and drain N⁺ regions 116 a and 116 b is a channel region 117. A gate insulating layer 118 is formed so as to surround the channel region 117, and a gate conductor layer 119 is formed so as to surround the gate insulating layer 118. In an SGT, the source and drain N⁺ regions 116 a and 116 b, the channel region 117, the gate insulating layer 118, and the gate conductor layer 119 are formed in a single Si pillar 115. Therefore, the area of the surface of the SGT appears to be equal to the area of one source or drain N⁺ region of a planar MOS transistor. Thus, circuit chips including SGTs can achieve further chip-size reduction compared with circuit chips including planar MOS transistors.

FIG. 16 is a sectional view of a CMOS inverter circuit including SGTs (e.g., refer to FIG. 38(b) in U.S. Patent Application Publication No. 2010/0264484).

In this CMOS inverter circuit, an i layer 121 (the “i layer” refers to an intrinsic Si layer) is formed on an insulating layer substrate 120, and a Si pillar SP1 for a P-channel SGT and a Si pillar SP2 for an N-channel SGT are formed on the i layer 121.

A drain P⁺ region 122 of the P-channel SGT is formed in the same layer as the i layer 121 so as to surround a lower portion of the Si pillar SP1 in plan view. A drain N⁺ region 123 of the N-channel SGT is formed in the same layer as the i layer 121 so as to surround a lower portion of the Si pillar SP2 in plan view.

A source P⁺ region 124 of the P-channel SGT is formed in a top portion of the Si pillar SP1, and a source N⁺ region 125 of the N-channel SGT is formed in a top portion of the Si pillar SP2.

Gate insulating layers 126 a and 126 b are formed on upper surfaces of the P⁺ region 122 and N⁺ region 123 so as to extend along and surround the Si pillars SP1 and SP2. A gate conductor layer 127 a of the P-channel SGT and a gate conductor layer 127 b of the N-channel SGT are formed so as to surround the gate insulating layers 126 a and 126 b.

Sidewall nitride films 128 a and 128 b serving as insulating layers are formed so as to surround the gate conductor layers 127 a and 127 b. Similarly, sidewall nitride films 128 c and 128 d serving as insulating layers are formed so as to surround a P⁺ region and an N⁺ region in top portions of the Si pillars SP1 and SP2.

The drain P⁺ region 122 of the P-channel SGT and the drain N⁺ region 123 of the N-channel SGT are connected to each other through a silicide layer 129 b. A silicide layer 129 a is formed on the source P⁺ region 124 of the P-channel SGT, and a silicide layer 129 c is formed on the source N⁺ region 125 of the N-channel SGT. Furthermore, silicide layers 129 d and 129 e are formed in top portions of the gate conductor layers 127 a and 127 b.

An i layer 130 a of the Si pillar SP1 that lies between the P⁺ regions 122 and 124 functions as a channel of the P-channel SGT. An i layer 130 b of the Si pillar SP2 that lies between the N⁺ regions 123 and 125 functions as a channel of the N-channel SGT.

A SiO₂ layer 131 is formed so as to cover the insulating layer substrate 120, the i layer 121, and the Si pillars SP1 and SP2. Furthermore, contact holes 132 a, 132 b, and 132 c are formed so as to extend through the SiO₂ layer 131. The contact hole 132 a is formed on the Si pillar SP1, the contact hole 132 c is formed on the Si pillar SP2, and the contact hole 132 b is formed on the drain P⁺ region 122 of the P-channel SGT and the N⁺ region 123 of the N-channel SGT.

A power supply wiring metal layer Vd formed on the SiO₂ layer 131 is connected to the source P⁺ region 124 of the P-channel SGT and the silicide layer 129 a through the contact hole 132 a. An output wiring metal layer Vo formed on the SiO₂ layer 131 is connected to the drain P⁺ region 122 of the P-channel SGT, the drain N⁺ region 123 of the N-channel SGT, and the silicide layer 129 b through the contact hole 132 b. A ground wiring metal layer Vs formed on the SiO₂ layer 131 is connected to the source N⁺ region 125 of the N-channel SGT and the silicide layer 129 c through the contact hole 132 c.

The gate conductor layer 127 a of the P-channel SGT and the gate conductor layer 127 b of the N-channel SGT are connected to an input wiring metal layer (not illustrated) while being connected to each other.

In this CMOS inverter circuit, the P-channel SGT and the N-channel SGT are formed in the Si pillars SP1 and SP2. Therefore, the circuit area is reduced when vertically viewed in plan. As a result, a further reduction in the size of the circuit is achieved compared with CMOS inverter circuits including known planar MOS transistors.

The CMOS inverter circuit including SGTs illustrated in FIG. 16 has also been required to have higher density and higher performance. However, the following problems arise when the density and performance of this circuit are further improved.

1. In the mask design for the Si pillars SP1 and SP2 and the i layer 121, margins need to be left in terms of shape and positional relationship to accurately form the Si pillars SP1 and SP2 on the i layer 121 with certainty. This inhibits the increase in the density of the circuit.

2. The resistances between the end of the silicide layer 129 b and the P⁺ region 122 directly below the Si pillar SP1 and between the end of the silicide layer 129 b and the N⁺ region 123 directly below the Si pillar SP2 decrease the driving current and the driving speed.

3. A thin gate insulating layer 126 a lies between the gate conductor layer 127 a and the P⁺ region 122. Therefore, a large coupling capacitance is present between the gate conductor layer 127 a and the P⁺ region 122. Similarly, a thin gate insulating layer 126 b lies between the gate conductor layer 127 b and the N⁺ region 123. Therefore, a large coupling capacitance is present between the gate conductor layer 127 b and the N⁺ region 123. Such large coupling capacitances inhibit the increase in the speed.

4. Thin sidewall nitride films 128 a and 128 b lie between the contact hole 132 b and the gate conductor layers 127 a and 127 b. Therefore, large coupling capacitances are present between the gate conductor layers 127 a and 127 b and the output wiring metal layer Vo. Such large coupling capacitances inhibit the increase in the speed. If the coupling capacitance is decreased by increasing the thicknesses of the sidewall nitride films 128 a and 128 b, the circuit area increases.

Accordingly, the density and performance of the circuit need to be improved by addressing the above problems.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method for producing a pillar-shaped semiconductor device that improves the density and performance of a circuit.

A method for producing a pillar-shaped semiconductor device according to a first aspect of the present invention includes a step of providing a structure including a substrate, a first semiconductor pillar that stands on a plane of the substrate in a vertical direction, and a first impurity region that is in contact with a lower portion of the first semiconductor pillar or a side surface of the lower portion and contains a donor or acceptor impurity atom; a step of forming a first material layer that has conductivity, extends in a horizontal direction, and is connected to, in plan view, at least one of an entire periphery of the first impurity region and an entire periphery of a first conductor layer surrounding a first insulating layer surrounding the first semiconductor pillar; a step of forming, on the first material layer, a second material layer that surrounds the first semiconductor pillar in plan view; a step of forming, on the first material layer, a third material layer that is partly connected to the second material layer in plan view; and a step of etching the first material layer using the second material layer and the third material layer as masks. A first region of the first material layer that surrounds the first semiconductor pillar in plan view is formed below the second material layer, and a second region of the first material layer that is partly connected to the first region in plan view is formed below the third material layer.

The second material layer is preferably formed so as to surround the first semiconductor pillar in a tubular shape with an equal width.

The first material layer preferably contains a semiconductor atom, a metal atom, and the donor or acceptor impurity atom.

The first material layer is preferably formed of a semiconductor layer containing the donor or acceptor impurity atom or a metal layer.

The step of providing a structure preferably includes a step of forming the first impurity region by performing heat treatment to force the donor or acceptor impurity atom toward an inside of the first semiconductor pillar from the first material layer containing the donor or acceptor impurity atom.

The method preferably includes a step of forming the first impurity region before formation of the first semiconductor pillar.

The second material layer is preferably formed of at least the first insulating layer and the first conductor layer.

The second material layer is preferably formed of a second insulating layer that surrounds an entire periphery of the first conductor layer, and the first material layer is preferably connected to an entire periphery of the first conductor layer in plan view.

The first region of the first material layer preferably includes a third region that is connected to the first impurity region and surrounds a part or entirety of the first semiconductor pillar and a fourth region that surrounds an entire periphery of the first conductor layer so as to be in contact with the entire periphery of the first conductor layer. The second region of the first material layer preferably includes a fifth region that is partly connected to the third region and extends in the horizontal direction and a sixth region that is partly connected to the fourth region and extends in the horizontal direction. The fifth region and the sixth region are preferably formed so as to be away from each other or to partly overlap each other in plan view.

The method preferably includes a step of entirely forming a third insulating layer after the structure is provided and a step of forming a first contact hole that extends through the third insulating layer. At least a surface layer of the second material layer preferably serves as an etching stopper for an etchant used for forming the first contact hole.

An upper surface of the third material layer is preferably positioned lower than a top of the first semiconductor pillar in the vertical direction.

The method preferably includes a step of forming a fourth material layer on the first material layer on a periphery of the first semiconductor pillar, the fourth material layer having a flat upper surface that is flush with or is positioned higher than an upper surface of a top of the first semiconductor pillar; a step of forming, on the fourth material layer, a fifth material layer that partly overlaps the first region in plan view; and a step of forming a sixth material layer by etching the fourth material layer using the fifth material layer as a mask. The third material layer is preferably formed by performing etching using both the fifth material layer and the sixth material layer as masks or the sixth material layer as a mask.

The method preferably includes a step of etching the fourth material layer having conductivity such that the fourth material layer has an upper surface positioned lower than the top of the first semiconductor pillar and a step of forming a second contact hole such that the second contact hole is in contact with the sixth material layer.

The method preferably includes a step of forming a second semiconductor pillar that is adjacent to the first semiconductor pillar; a step of forming, on the first material layer, a seventh material layer that surrounds the second semiconductor pillar in plan view; a step of forming the third material layer that is partly connected to each of the second material layer and the seventh material layer in plan view; and a step of etching the first material layer using the second material layer, the third material layer, and the seventh material layer as masks. The first region of the first material layer that surrounds the first semiconductor pillar in plan view is preferably formed below the second material layer, a seventh region of the first material layer that surrounds the second semiconductor pillar in plan view is preferably formed below the seventh material layer, and the second region of the first material layer that is partly connected to each of the first region and the seventh region in plan view is preferably formed below the third material layer.

The second material layer and the seventh material layer are preferably formed in a connected manner between the first semiconductor pillar and the second semiconductor pillar in plan view. The method preferably further includes a step of etching the first material layer using the second material layer and the seventh material layer as masks.

a part contacted with the side surface of the first semiconductor pillar or entirety of the first material layer is formed with a single crystal layer containing donor or acceptor impurity atoms.

the single crystal semiconductor layer is formed as the first impurity region.

A part or entirety of the first impurity region is preferably formed on the side surface of the lower portion of the first semiconductor pillar by an epitaxial crystal growth method.

A part or entirety of the first impurity region is preferably formed on the side surface of the lower portion of the first semiconductor pillar by a selective epitaxial crystal growth method.

The method preferably includes a step of partly etching the first impurity region using the second material layer as a mask in plan view.

The method preferably includes a step of forming the first impurity region by the epitaxial crystal growth method such that a periphery of the first impurity region in plan view is present inward with respect to a periphery of the second material layer;

a step of forming a fourth material layer that has conductivity and is in contact with a side surface of the first impurity region; and

a step of etching the fourth material layer using the second material layer as a mask.

The present invention can provide a method for producing a semiconductor device including an SGT for improving the density and performance of a circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1AA to 1AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a first embodiment.

FIGS. 1BA to 1BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a first embodiment.

FIGS. 1CA to 1CD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a first embodiment.

FIGS. 1DA to 1DD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a first embodiment.

FIGS. 1EA to 1ED are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a first embodiment.

FIGS. 1FA to 1FD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a first embodiment.

FIGS. 1GA to 1GD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a first embodiment.

FIGS. 1HA to 1HD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a first embodiment.

FIGS. 1IA to 1ID are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a first embodiment.

FIGS. 1JA to 1JE are plan views and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a first embodiment.

FIGS. 2AA to 2AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a second embodiment.

FIGS. 2BA to 2BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a second embodiment.

FIGS. 2CA to 2CE are plan views and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a second embodiment.

FIGS. 3AA to 3AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a third embodiment.

FIGS. 3BA to 3BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a third embodiment.

FIGS. 3CA to 3CD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a third embodiment.

FIGS. 3DA to 3DD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a third embodiment.

FIGS. 3EA to 3ED are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a third embodiment.

FIGS. 3FA to 3FD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a third embodiment.

FIGS. 4AA to 4AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fourth embodiment.

FIGS. 4BA to 4BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fourth embodiment.

FIGS. 4CA to 4CD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fourth embodiment.

FIGS. 4DA to 4DD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fourth embodiment.

FIGS. 5AA to 5AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fifth embodiment.

FIGS. 5BA to 5BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fifth embodiment.

FIGS. 5CA to 5CD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fifth embodiment.

FIGS. 5DA to 5DD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fifth embodiment.

FIGS. 6AA to 6AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a sixth embodiment.

FIGS. 6BA to 6BE are plan views and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a sixth embodiment.

FIGS. 7AA to 7AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a seventh embodiment.

FIGS. 7BA to 7BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a seventh embodiment.

FIGS. 7CA to 7CD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a seventh embodiment.

FIGS. 8A to 8D are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to an eighth embodiment.

FIGS. 9AA to 9AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a ninth embodiment.

FIGS. 9BA to 9BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a ninth embodiment.

FIGS. 10AA to 10AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a tenth embodiment.

FIGS. 10BA to 10BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a tenth embodiment.

FIGS. 10CA to 10CD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a tenth embodiment.

FIGS. 10DA to 10DD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a tenth embodiment.

FIGS. 10EA to 10ED are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a tenth embodiment.

FIGS. 10FA to 10FD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a tenth embodiment.

FIGS. 11AA to 11AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to an eleventh embodiment.

FIGS. 11BA to 11BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to an eleventh embodiment.

FIGS. 11CA to 11CD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to an eleventh embodiment.

FIGS. 12AA to 12AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a twelfth embodiment.

FIGS. 12BA to 12BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a twelfth embodiment.

FIGS. 12CA to 12CD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a twelfth embodiment.

FIGS. 12DA to 12DD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a twelfth embodiment.

FIGS. 13AA to 13AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a thirteenth embodiment.

FIGS. 13BA to 13BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a thirteenth embodiment.

FIGS. 14AA to 14AD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fourteenth embodiment.

FIGS. 14BA to 14BD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fourteenth embodiment.

FIGS. 14CA to 14CD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fourteenth embodiment.

FIGS. 14DA to 14DD are a plan view and sectional views illustrating a CMOS inverter circuit for describing a method for producing a semiconductor device including an SGT according to a fourteenth embodiment.

FIG. 15 schematically illustrates a structure of a known SGT.

FIG. 16 is a sectional view of a CMOS inverter circuit including a known SGT.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereafter, a method for producing a semiconductor device including an SGT according to embodiments of the present invention will be described with reference to the attached drawings.

First Embodiment

FIG. 1AA to FIG. 1JE illustrate a method for producing a CMOS inverter circuit including an SGT according to a first embodiment of the present invention.

FIGS. 1AA to 1AD are a plan view and sectional views for describing the first production process of the CMOS inverter circuit including an SGT. FIG. 1AA is a plan view, FIG. 1AB is a sectional view taken along line X-X′ in FIG. 1AA, FIG. 1AC is a sectional view taken along line Y1-Y1′ in FIG. 1AA, and FIG. 1AD is a sectional view taken along line Y2-Y2′ in FIG. 1AA. In other figures referred to in the description below, the same applies to the relationship of views indicated by the suffixes A, B, C, and D.

As illustrated in FIGS. 1AA to 1AD, SiO₂ layers 2 a and 2 b, SiN layers 3 a and 3 b, and resist layers 5 a and 5 b are formed by depositing a SiO₂ layer (not illustrated) and a silicon nitride layer (SiN layer, a Si₃N₄ film is often used, not illustrated) on an i layer substrate 1 and using a lithography technique and, for example, reactive ion etching (RIE). The SiO₂ layer 2 a, the SiN layer 3 a, and the resist layer 5 a are stacked on the i layer substrate 1 in this order. The SiO₂ layer 2 b, the SiN layer 3 b, and the resist layer 5 b are stacked on the i layer substrate 1 in this order.

Next, as illustrated in FIGS. 1BA to 1BD, the i layer substrate 1 is etched by, for example, RIE using the SiO₂ layers 2 a and 2 b, the SiN layers 3 a and 3 b, and the resist layers 5 a and 5 b as etching masks. Thus, a lower portion of the i layer substrate 1 is left as an i layer substrate 1 a and Si pillars 4 a and 4 b are formed on the i layer substrate 1 a. The resist layers 5 a and 5 b are removed. The Si pillar 4 a is located below the SiO₂ layer 2 a and the SiN layer 3 a, and the Si pillar 4 b is located below the SiO₂ layer 2 b and the SiN layer 3 b. A thin SiO₂ layer (not illustrated) is formed on side surfaces of the Si pillars 4 a and 4 b and a surface of the i layer substrate 1 a by, for example, an atomic layer deposition (ALD) method or an oxidation method.

Next, as illustrated in FIGS. 1CA to 1CD, for example, a bias sputtering process is carried out in the following manner: a substrate metal plate on which the i layer substrate 1 a is disposed and a facing metal plate located away from the substrate metal plate are provided; a direct-current voltage is applied to the substrate metal plate, and an RF voltage is applied across these two parallel metal plates, to thereby sputter the material atoms of the facing metal plate onto the i layer substrate 1 a. Thus, a SiO₂ layer 6, a WSi₂ layer 7, and a SiO₂ layer 8 are formed. Subsequently, a lower SiO₂ layer (not illustrated), a WSi₂ layer (not illustrated), and an upper SiO₂ layer (not illustrated) formed on the Si pillars 4 a and 4 b are removed. Since the Si pillars 4 a and 4 b are formed by RIE, the side surfaces of the Si pillars 4 a and 4 b are substantially vertical to the plane of the i layer substrate 1 a. Therefore, a SiO₂ film, a WSi₂ film, and a SiO₂ film are not formed on the side surfaces of the Si pillars 4 a and 4 b (for the mechanism in which material atoms do not adhere to the side surfaces, refer to C. Y. Ting, V. J. Vivalda, and H. G. Schaefer: “Study of planarized sputter-deposited SiO₂” J. Vac. Sci. Technology, 15(3), May/June (1978)).

Next, as illustrated in FIGS. 1DA to 1DD, a resist layer 10 is formed so as to cover the Si pillar 4 b. Boron ions (B⁺) are implanted in a direction toward the upper surface of the i layer substrate 1 a using the resist layer 10 as a mask to form a WSi₂ layer 7 a containing B atoms on the periphery of the Si pillar 4 a. The resist layer 10 is removed.

Subsequently, arsenic ions (As⁺) are implanted using, as a mask, a resist layer (not illustrated) formed so as to cover the Si pillar 4 a. Thus, a WSi₂ layer 7 b containing As atoms is formed on the periphery of the Si pillar 4 b. The resist layer is removed. A SiO₂ film (not illustrated) is entirely deposited by chemical vapor deposition (CVD). The SiO₂ film is etched by RIE so that a part of the SiO₂ film is left on the side surfaces of the Si pillars 4 a and 4 b. Thus, as illustrated in FIGS. 1EA to 1ED, SiO₂ layers 11 a and 11 b are formed on the side surfaces of the Si pillars 4 a and 4 b.

Next, as illustrated in FIGS. 1FA to 1FD, by performing heat treatment, the B atoms are forced toward the inside of the Si pillar 4 a from the WSi₂ layer 7 a to form a P⁺ region 12 a in the Si pillar 4 a, and the As atoms are forced toward the inside of the Si pillar 4 b from the WSi₂ layer 7 b to form an N⁺ region 12 b in the Si pillar 4 b (for the mechanism in which the P⁺ region 12 a and the N⁺ region 12 b are formed through the forcing phenomenon of impurity atoms, refer to V. Probst, H. Schaber, A. Mitwalsky, and H. Kabza: “WSi₂ and CoSi₂ as diffusion sources for shallow-junction formation in silicon”, J. Appl. Phys. Vol. 70(2), No. 15, pp. 708-719 (1991)).

Next, as illustrated in FIGS. 1GA to 1GD, a resist layer 13 is formed so as to partly cover the Si pillars 4 a and 4 b. Then, the SiO₂ layer 8 and the WSi₂ layers 7 a and 7 b are etched by RIE using the resist layer 13, the SiN layers 3 a and 3 b, and the SiO₂ layers 11 a and 11 b as masks to form a SiO₂ layer 8 a and WSi₂ layers 7 aa and 7 bb. In this case, the WSi₂ layers 7 aa and 7 bb lie below the SiO₂ layers 11 a and 11 b, and are constituted by first alloy layers that surround the entire peripheries of the Si pillars 4 a and 4 b in plan view and a second alloy layer that is connected to the first alloy layers and lies below the resist layer 13. The first alloy layers of the WSi₂ layers 7 a and 7 b are self-aligned with the P⁺ region 12 a and the N⁺ region 12 b. That is, the first alloy layers of the WSi₂ layers 7 aa and 7 bb that lie below the SiO₂ layers 11 a and 11 b are formed in a tubular shape with an equal width so as to surround the entire peripheries of the P⁺ region 12 a and the N⁺ region 12 b regardless of the mask misalignment in lithography during formation of the resist layer 13.

Next, the resist layer 13 is removed. Then, as illustrated in FIGS. 1HA to 1HD, a SiO₂ film (not illustrated) is entirely deposited by CVD and etched back to a position of an upper surface of the SiO₂ layer 8 a to form a SiO₂ layer 14 (the upper surface of the SiO₂ layer 14 may be positioned higher than the upper surface of the SiO₂ layer 8 a). The SiO₂ layers 11 a and 11 b left on the side surfaces of the Si pillars 4 a and 4 b are removed. A HfO₂ layer 15 and a TiN layer 16 are entirely deposited by atomic layer deposition (ALD).

Next, as illustrated in FIGS. 1IA to 1ID, a SiO₂ film (not illustrated) is entirely deposited by CVD and etched back until the upper surface of the SiO₂ film is positioned lower than the tops of the Si pillars 4 a and 4 b to form a SiO₂ layer 18. Portions of the TiN layer 16, the HfO₂ layer 15, the SiN layers 3 a and 3 b, and the SiO₂ layers 2 a and 2 b positioned higher than the upper surface of the SiO₂ layer 18 are removed. The remaining portions of the TiN layer 16 and the HfO₂ layer 15 are referred to as a TiN layer 16 a and a HfO₂ layer 15 a. By performing lithography and ion implantation, a P⁺ region 19 a is formed in a top portion of the Si pillar 4 a and an N⁺ region 19 b is formed in a top portion of the Si pillar 4 b.

Next, as illustrated in FIGS. 1JA to 1JD, a SiO₂ layer 21 is formed on the SiO₂ layer 18 so as to cover the P⁺ region 19 a and the N⁺ region 19 b. A contact hole 22 a is formed on the P⁺ region 19 a, a contact hole 22 b is formed on the N⁺ region 19 b, a contact hole 22 c is formed on the TiN layer 16 a, and a contact hole 22 d that is connected to the upper surfaces and side surfaces of the WSi₂ layers 7 aa and 7 bb is formed. A power supply wiring metal layer Vdd connected to the P⁺ region 19 a through the contact hole 22 a is formed on the SiO₂ layer 21. A ground wiring metal layer Vss connected to the N⁺ region 19 b through the contact hole 22 b is formed on the SiO₂ layer 21. An input wiring metal layer Vin connected to the TiN layer 16 a through the contact hole 22 c is formed on the SiO₂ layer 21. An output wiring metal layer Vout connected to the WSi₂ layers 7 aa and 7 bb through the contact hole 22 d is formed on the SiO₂ layer 21. The thickness of the WSi₂ layers 7 aa and 7 bb is desirably larger than the length of one side of the contact hole 22 d in plan view. This reduces the contact resistance, on the side surfaces of the WSi₂ layers 7 aa and 7 bb, between the WSi₂ layers 7 aa and 7 bb and the output wiring metal layer Vout that is connected to the WSi₂ layers 7 aa and 7 bb through the contact hole 22 d.

Thus, a CMOS inverter circuit constituted by a P-channel SGT for load and an N-channel SGT for drive is formed. The P-channel SGT for load includes the P⁺ region 12 a as a source, the P⁺ region 19 a as a drain, the HfO₂ layer 15 a as a gate insulating layer, the TiN layer 16 a as a gate conductor layer, and a portion of the Si pillar 4 a between the P⁺ regions 12 a and 19 a as a channel. The N-channel SGT for drive includes the N⁺ region 12 b as a source, the N⁺ region 19 b as a drain, the HfO₂ layer 15 a as a gate insulating layer, the TiN layer 16 a as a gate conductor layer, and a portion of the Si pillar 4 b between the N⁺ regions 12 b and 19 b as a channel.

FIG. 1JE illustrates the relationship between the Si pillars 4 a and 4 b, the P⁺ region 12 a, the N⁺ region 12 b, and the WSi₂ layers 7 aa and 7 bb in plan view. The diagonally shaded area indicates the WSi₂ layers 7 aa and 7 bb. The WSi₂ layer 7 aa is constituted by a WSi₂ layer 7Aa serving as a first alloy layer that surrounds the entire periphery of the Si pillar 4 a in a tubular shape with an equal width and is formed in a self-aligned manner with the P⁺ region 12 a and a WSi₂ layer 7Ab serving as a second alloy layer that is partly in contact with the periphery of the WSi₂ layer 7Aa in a connected manner. Similarly, the WSi₂ layer 7 bb is constituted by a WSi₂ layer 7Ba serving as a first alloy layer that surrounds the entire periphery of the Si pillar 4 b in a tubular shape with an equal width and is formed in a self-aligned manner with the N⁺ region 12 b and a WSi₂ layer 7Bb serving as a second alloy layer that is partly in contact with the periphery of the WSi₂ layer 7Ba in a connected manner. The WSi₂ layers 7Ab and 7Bb are in contact with each other.

The first embodiment provides the following advantages.

1. In the production method according to this embodiment, as illustrated in FIG. 1JE, the WSi₂ layers 7Aa and 7Ba are formed as first alloy layers that are directly in contact with the side surfaces of the Si pillars 4 a and 4 b, that surround the entire peripheries of the Si pillars 4 a and 4 b in a tubular shape with an equal width in plan view, and that are in contact with the P⁺ region 12 a and the N⁺ region 12 b in a self-aligned manner. The presence of the WSi₂ layers 7Aa and 7Ba serving as low-resistance first alloy layers that surround the entire peripheries of the Si pillars 4 a and 4 b can generate a uniform electric field in the P⁺ region 12 a and the N⁺ region 12 b during circuit operation. This uniform electric field can be generated regardless of the planar shape of the WSi₂ layers 7Ab and 7Bb serving as second alloy layers. The WSi₂ layers 7Ab and 7Bb serving as second alloy layers may be connected to any parts of the peripheries of the WSi₂ layers 7Aa and 7Ba serving as first alloy layers. Thus, in terms of design, the WSi₂ layers 7Ab and 7Bb serving as second alloy layers may be formed without surrounding the Si pillars 4 a and 4 b. This can increase the density of a circuit and improve the performance of the circuit.

2. In the related art, there has been a need to form the Si pillars SP1 and SP2 on the i layer 121 and introduce an impurity into the i layer 121 to form the P⁺ region 122 and the N⁺ region 123 as illustrated in FIG. 15. Therefore, in the mask design for the Si pillars SP1 and SP2 and the i layer 121, margins need to be left in terms of shape and positional relationship to accurately form the Si pillars SP1 and SP2 on the i layer 121 with certainty. This inhibits the increase in the density of the circuit. In contrast, in this embodiment, a region that corresponds to the i layer 121 and has been required in the related art is unnecessary. This can further increase the density of a circuit.

3. In this embodiment, the WSi₂ layers 7 a and 7 b containing acceptor and donor impurities, which will be changed into the WSi₂ layers 7 aa and 7 bb in a process performed later, are source layers for supplying acceptor and donor impurities used for forming the P⁺ regions 12 a and the N⁺ region 12 b in the Si pillars 4 a and 4 b. The WSi₂ layers 7 aa and 7 bb in a completed circuit are formed in a self-aligned manner with the P⁺ region 12 a and the N⁺ region 12 b and serve as wiring conductor layers directly connected to the P⁺ region 12 a and the N⁺ region 12 b. This simplifies the production process of a circuit.

4. In the related art, as illustrated in FIG. 15, the P⁺ region 122 and the N⁺ region 123 formed in the i layer 121 are formed so as to expand to the bottom portions of the Si pillars SP1 and SP2 and are connected to the output wiring metal layer Vo through the contact hole 132 b formed on the low-resistance silicide layer 129 b formed on the upper surface of the i layer 121. Therefore, a resistance is generated in a portion of the P⁺ region 122 between the end of the silicide layer 129 b and a position directly below the Si pillar SP1 and in a portion of the N⁺ region 123 between the end of the silicide layer 129 b and a position directly below the Si pillar SP2, which reduces the driving current and the driving speed. In contrast, in this embodiment, the WSi₂ layers 7 aa and 7 bb serving as low-resistance silicide layers are directly connected to the P⁺ region 12 a and the N⁺ region 12 b on the side surfaces of the Si pillars 4 a and 4 b. This prevents formation of a resistance region formed in a portion of the P⁺ region 122 between the end of the silicide layer 129 b and a position directly below the Si pillar SP1 and in a portion of the N⁺ region 123 between the end of the silicide layer 129 b and a position directly below the Si pillar SP2 in the related art.

5. In the related art, as is clear from FIG. 15, the planar area of the contact hole 132 b that connects the output wiring metal layer Vo and the P⁺ region 122 and N⁺ region 123 decreases with increasing the density of the circuit, which increases the contact resistance. In particular, when a high-density semiconductor circuit is formed, the contact hole is formed with a minimum size in plan view to increase the density. Therefore, the increase in the contact resistance is disadvantageous. In contrast, in this embodiment, the output wiring metal layer Vout is connected to the upper surfaces and side surfaces of the WSi₂ layers 7 aa and 7 bb in the contact hole 22 d. Since the entire WSi₂ layers 7 aa and 7 bb are formed of a low-resistance silicide material, the contact resistance can be reduced by increasing the thicknesses of the WSi₂ layers 7 aa and 7 bb in the vertical direction without enlarging the shape of the contact hole 22 d in plan view.

6. In the description of this embodiment, the contact hole 22 d through which the output wiring metal layer Vout is connected is formed so as to be in contact with both the WSi₂ layers 7 aa and 7 bb. However, the WSi₂ layer 7 aa containing an acceptor impurity atom and the WSi₂ layer 7 bb containing a donor impurity atom are both low-resistance silicide layers, and therefore even if the contact hole 22 d is formed on only one of the WSi₂ layers 7 aa and 7 bb, the P⁺ region 12 a and N⁺ region 12 b can be connected to the output wiring metal layer Vout at a low resistance. This can increase the degree of freedom of the position of the contact hole 22 d in the circuit design, which increases the density of the circuit.

Modification of First Embodiment

A SiN layer may be disposed as an etching stop layer between the WSi₂ layer 7 and the SiO₂ layer 8. This can prevent etching of the WSi₂ layer with certainty when the SiO₂ layer entirely deposited to form the SiO₂ layers 11 a and 11 b is etched. This structure is applicable to other embodiments below.

Second Embodiment

FIG. 2AA to FIG. 2CE illustrate a method for producing a CMOS inverter circuit including an SGT according to a second embodiment of the present invention. Among FIG. 2AA to FIG. 2CD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1′ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2′ in the corresponding figures suffixed with A. FIG. 2CE illustrates the relationship between Si pillars 4 a and 4 b, a P⁺ region 12 a, an N⁺ region 12 b, and CoSi₂ layers 23 aa and 23 bb in plan view.

As illustrated in FIGS. 2AA to 2AD, instead of the WSi₂ layers 7 a and 7 b in FIGS. 1EA to 1ED of the first embodiment, a CoSi₂ layer 23 a containing an acceptor impurity is formed on the periphery of the Si pillar 4 a and a CoSi₂ layer 23 b containing a donor impurity is formed on the periphery of the Si pillar 4 b.

Next, as illustrated in FIGS. 2BA to 2BD, by performing heat treatment, CoSi₂ layers 24 a and 24 b are formed on the side surfaces of the Si pillars 4 a and 4 b through silicidation. A P⁺ region 12 a is formed in the Si pillar 4 a through the forcing phenomenon of B atoms from the CoSi₂ layers 23 a and 24 a. An N⁺ region 12 b is formed in the Si pillar 4 b through the forcing phenomenon of As atoms from the CoSi₂ layers 23 b and 24 b (for the mechanism in which the CoSi₂ layers 24 a and 24 b, the P⁺ region 12 a, and the N⁺ region 12 b are formed through the forcing phenomenon of impurity atoms, refer to V. Probst, H. Schaber, A. Mitwalsky, and H. Kabza: “WSi₂ and CoSi₂ as diffusion sources for shallow-junction formation in silicon”, J. Appl. Phys. Vol. 70(2), No. 15, pp. 708-719 (1991)).

Then, by performing the same processes as those in the first embodiment, a CMOS inverter circuit illustrated in FIGS. 2CA to 2CD is formed. The P⁺ region 12 a and the N⁺ region 12 b are formed in lower portions of the Si pillars 4 a and 4 b. The CoSi₂ layers 24 a and 24 b are formed on the side surfaces of the Si pillars 4 a and 4 b so as to surround the entire peripheries of the P⁺ region 12 a and the N⁺ region 12 b. The CoSi₂ layers 23 aa and 23 bb are formed so as to surround the entire peripheries of the CoSi₂ layers 24 a and 24 b.

FIG. 2CE illustrates the relationship between the Si pillars 4 a and 4 b, the P⁺ region 12 a, the N⁺ region 12 b, the CoSi₂ layers 24 a and 24 b formed inside the Si pillars 4 a and 4 b, and the CoSi₂ layers 23 aa and 23 bb that surround the entire peripheries of the Si pillars 4 a and 4 b in plan view. The diagonally shaded area indicates the CoSi₂ layers 23 aa and 23 bb. The CoSi₂ layer 23 aa is constituted by a CoSi₂ layer 23Aa serving as a first alloy layer that surrounds the entire periphery of the Si pillar 4 a in a tubular shape with an equal width and is formed in a self-aligned manner with the P⁺ region 12 a and a CoSi₂ layer 23Ab serving as a second alloy layer that is partly connected to the periphery of the CoSi₂ layer 23Aa. The CoSi₂ layer 23 bb is constituted by a CoSi₂ layer 23Ba serving as a first alloy layer that surrounds the entire periphery of the Si pillar 4 b in a tubular shape with an equal width and is formed in a self-aligned manner with the N⁺ region 12 b and a CoSi₂ layer 23Bb serving as a second alloy layer that is partly connected to the periphery of the CoSi₂ layer 23Ba. The CoSi₂ layer 24 a serving as a third alloy layer is formed inside the Si pillar 4 a so as to be connected to the entire inner periphery of the CoSi₂ layer 23Aa serving as a first alloy layer. At the same time, the CoSi₂ layer 24 b serving as a third alloy layer is formed inside the Si pillar 4 b so as to be connected to the entire inner periphery of the CoSi₂ layer 23Ba.

This embodiment provides the following advantage.

In this embodiment, the CoSi₂ layer 24 a and the CoSi₂ layer 23Aa serving as a first alloy layer are formed so as to surround the entire periphery of the P⁺ region 12 a in a tubular shape with an equal width. Similarly, the CoSi₂ layer 24 b serving as a third alloy layer and the CoSi₂ layer 23Ba serving as a first alloy layer are formed so as to surround the entire periphery of the N⁺ region 12 b in a tubular shape with an equal width. Thus, an electric field is uniformly applied to the P⁺ region 12 a and the N⁺ region 12 b, and the source or drain resistance in the bottom portion of the Si pillar can be reduced compared with in the first embodiment.

Third Embodiment

FIG. 3AA to FIG. 3FD illustrate a method for producing a CMOS inverter circuit including an SGT according to a third embodiment of the present invention. Among FIG. 3AA to FIG. 3FD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1′ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2′ in the corresponding figures suffixed with A.

As illustrated in FIGS. 3AA to 3AD, Si pillars 4 a and 4 b are formed on the i layer substrate 1 a by RIE using a resist layer (not illustrated), the SiN layers 3 a and 3 b, and the SiO₂ layers 2 a and 2 b as masks. Then, a SiO₂ layer 26 is entirely deposited by ALD. A SiN layer 27 is formed on the peripheries of the Si pillars 4 a and 4 b.

Next, as illustrated in FIGS. 3BA to 3BD, a resist layer 28 is formed on the SiN layer 27. Hydrogen fluoride (HF) gas is caused to flow throughout the substrate to etch the SiO₂ layer 26 that is in contact with the resist layer 28 (for the etching mechanism, refer to Tadashi Shibata, Susumu Kohyama, and Hisakazu Iizuka: “A New Field Isolation Technology for High Density MOS LSI”, Japanese Journal of Applied Physics, Vol. 18, pp. 263-267 (1979)).

Next, as illustrated in FIG. 3CA to 3CD, as a result of the etching of the SiO₂ layer 26, holes 30 a and 30 b are formed in lower portions of the Si pillars 4 a and 4 b in a tubular shape. Thus, the SiO₂ layer 26 is divided into SiO₂ layers 26 a and 26 b that surround upper portions of the Si pillars 4 a and 4 b and a SiO₂ layer 26 c that surrounds lower portions of the Si pillars 4 a and 4 b and lies on the i layer substrate 1 a. The resist layer 28 is removed. A WSi₂ layer 31 is formed on the SiN layer 27 so as to have an upper surface positioned higher than the holes 30 a and 30 b formed as a result of the etching of the SiO₂ layer 26. A SiO₂ layer 32 is formed on the WSi₂ layer 31.

Next, as illustrated in FIGS. 3DA to 3DD, a WSi₂ layer 31 a containing B atoms and a WSi₂ layer 31 b containing As atoms are formed through the same processes as those described in FIG. 1DA to FIG. 1ED of the first embodiment. By performing heat treatment, the B atoms in the WSi₂ layer 31 a are forced toward the inside of the Si pillar 4 a to form a P⁺ region 33 a and the As atoms in the WSi₂ layer 31 b are forced toward the inside of the Si pillar 4 b to form an N⁺ region 33 b.

Next, as illustrated in FIG. 3EA to 3ED, a resist layer 13 that partly covers the Si pillars 4 a and 4 b in plan view is formed through the same process as that described in FIGS. 1GA to 1GD of the first embodiment. The SiO₂ layer 32 and the WSi₂ layers 31 a and 31 b are etched by RIE using, as masks, the resist layer 13 and the SiO₂ layers 26 a and 26 b that cover the entire peripheries of the Si pillars 4 a and 4 b in plan view. Thus, WSi₂ layers 31 aa and 31 bb are formed below the SiO₂ layers 26 a and 26 b and the resist layer 13. A SiO₂ layer 32 a is left below the resist layer 13.

Next, as illustrated in FIGS. 3FA to 3FD, the resist layer 13 and the SiO₂ layers 26 a, 26 b, and 32 a are removed. A SiO₂ layer 35, a HfO₂ layer 36, and a TiN layer 37 are formed as in the case of the SiO₂ layer 14, the HfO₂ layer 15, and the TiN layer 16. Then, a CMOS inverter circuit is formed on the i layer substrate 1 a by performing the same processes as those in FIG. 1HA to FIG. 1JD of the first embodiment.

In this embodiment, the WSi₂ layers 31 aa and 31 bb, which are similar to the WSi₂ layers 7 aa and 7 bb, can be formed without forming the SiO₂ layers 11 a and 11 b on the side surfaces of the Si pillars 4 a and 4 b unlike in the first embodiment. Thus, the same advantages as those of the first embodiment are obtained.

Fourth Embodiment

FIG. 4AA to FIG. 4DD illustrate a method for producing a CMOS inverter circuit including an SGT according to a fourth embodiment of the present invention. Among FIG. 4AA to FIG. 4DD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1′ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2′ in the corresponding figures suffixed with A.

In the third embodiment, as illustrated in FIGS. 3CA to 3CD, the holes 30 a and 30 b are formed, in a tubular shape, in the lower portions of the SiO₂ layers 26 a and 26 b that cover the Si pillars 4 a and 4 b. On the other hand, in this embodiment, as illustrated in FIGS. 4AA to 4AD, a HfO₂ layer (not illustrated), a TiN layer (not illustrated), and a SiO₂ layer (not illustrated) formed on the SiN layer 27 so as to cover the Si pillars 4 a and 4 b are etched using HF gas in the same manner as in the third embodiment to form tubular holes 30A and 30B in lower portions of the Si pillars 4 a and 4 b. Thus, HfO₂ layers 15A and 15B, TiN layers 16A and 16B, and SiO₂ layers 38 a and 38 b are formed so as to cover the Si pillars 4 a and 4 b. Titanium oxide (TiO) layers 39 a and 39 b are formed on surfaces of the TiN layers 16A and 16B, the surfaces facing the holes 30A and 30B.

Next, as illustrated in FIGS. 4BA to 4BD, for example, a CoSi₂ layer (not illustrated) and a SiO₂ layer 40 are formed on the SiN layer 27 so as to each have an upper surface positioned higher than the holes 30A and 30B. As in the second embodiment, a CoSi₂ layer 41 a that surrounds the Si pillar 4 a and contains B atoms and a CoSi₂ layer 41 b that surrounds the Si pillar 4 b and contains As atoms are formed by ion implantation. By performing heat treatment, the B atoms in the CoSi₂ layer 41 a are forced toward the inside of the Si pillar 4 a to form a P⁺ region 42 a, and the As atoms in the CoSi₂ layer 41 b are forced toward the inside of the Si pillar 4 b to form an N⁺ region 42 b. At the same time, CoSi₂ layers 43 a and 43 b are formed in the peripheral portions of the Si pillars 4 a and 4 b that are in contact with the CoSi₂ layers 41 a and 41 b.

Next, as illustrated in FIGS. 4CA to 4CD, a resist layer 13 that partly overlaps the top portions of the SiO₂ layers 38 a and 38 b that cover the Si pillars 4 a and 4 b is formed as in the first embodiment. The SiO₂ layer 40 and the CoSi₂ layers 41 a and 41 b are etched by RIE using the resist layer 13 and the SiO₂ layers 38 a and 38 b as masks to form a SiO₂ layer 40 a and CoSi₂ layers 41 aa and 41 bb.

Subsequently, the resist layer 13 is removed. As illustrated in FIGS. 4DA to 4DD, a SiN layer 45 is then formed on the peripheries of the Si pillars 4 a and 4 b so as to have an upper surface positioned higher than the P⁺ region 42 a and the N⁺ region 42 b. Holes that surround the TiN layers 16A and 16B are formed in the SiO₂ layers 38A and 38B such that the upper surface of the SiN layer 45 is flush with the lower ends of the holes. For example, a NiSi layer 46 is formed on the SiN layer 45 so as to be connected to the TiN layers 16A and 16B. A SiO₂ layer 47 is formed on the SiN layer 45 and the NiSi layer 46 so as to have an upper surface positioned lower than the tops of the Si pillars 4 a and 4 b. A P⁺ region 19 a is formed in a top portion of the Si pillar 4 a and an N⁺ region 19 b is formed in a top portion of the Si pillar 4 b. A SiO₂ layer 21 is entirely formed. A contact hole 22 a is formed on the P⁺ region 19 a. A contact hole 22 b is formed on the N⁺ region 19 b. A contact hole 22C is formed on the NiSi layer 46. A contact hole 22 d that is connected to the upper surfaces and side surfaces of the CoSi₂ layers 41 aa and 41 bb is formed. A power supply wiring metal layer Vdd connected to the P⁺ region 19 a through the contact hole 22 a, a ground wiring metal layer Vss connected to the N⁺ region 19 b through the contact hole 22 b, an input wiring metal layer Vin connected to the NiSi layer 46 through the contact hole 22C, and an output wiring metal layer Vout connected to the CoSi₂ layers 41 aa and 41 bb through the contact hole 22 d are formed on the SiO₂ layer 21. Thus, a CMOS inverter circuit is formed on the i layer substrate 1 a.

This embodiment provides the following advantages.

1. In this embodiment, as described with reference to FIGS. 4CA to 4CD, the CoSi₂ layers 41 a and 41 b are etched using, as masks, the HfO₂ layers 15 a and 15 b, the TiN layers 16A and 16B, and the SiO₂ layers 38 a and 38 b that surround the Si pillars 4 a and 4 b to form CoSi₂ layers 41 aa and 41 bb that surround the entire peripheries of the Si pillars 4 a and 4 b in a tubular shape with an equal width. By using, as mask material layers, the HfO₂ layers 15 a and 15 b serving as gate insulating layers, the TiN layers 16A and 16B serving as gate conductor layers, and the SiO₂ layers 38 a and 38 b serving as gate protection layers, the process can be simplified.

2. In the first embodiment, the thin SiO₂ layer 8 a and the thin HfO₂ layer 15 a lie between the WSi₂ layers 7 aa and 7 bb connected to the P⁺ region 12 a and the N⁺ region 12 b serving as drain layers and the TiN layer 16 a serving as a gate conductor layer. Therefore, there is a large capacitance between the drain P⁺ region 12 a and N⁺ region 12 b and the gate TiN layer 16 a. This inhibits the increase in the speed of the CMOS inverter circuit. In contrast, in this embodiment, a thick SiN layer 45 is formed between the NiSi layer 46 connected to the gate TiN layers 16A and 16B and the CoSi₂ layers 41 aa and 41 bb connected to the drain P⁺ region 42 a and N⁺ region 42 b. This can reduce the capacitance between the NiSi layer 46 connected to the gate TiN layers 16A and 16B and the drain P⁺ region 42 a and N⁺ region 42 b. This increases the speed of the CMOS inverter circuit.

Modification of Fourth Embodiment

In this embodiment, the SiO₂ layer 40 and the CoSi₂ layers 41 a and 41 b are etched by RIE using the resist layer 13 and the SiO₂ layers 38 a and 38 b as masks to form the SiO₂ layer 40 a and the CoSi₂ layers 41 aa and 41 bb. Instead of the formation of the SiO₂ layers 38 a and 38 b, an appropriate etchant such as an etchant that etches TiN but not SiO₂ or CoSi₂ may be used in RIE. In this case, the SiO₂ layer 40 a and the CoSi₂ layers 41 aa and 41 bb can be formed using, as masks, the resist layer 13 and the TiN layers 16A and 16B serving as gate conductor layers.

Fifth Embodiment

FIG. 5AA to FIG. 5DD illustrate a method for producing a CMOS inverter circuit including an SGT according to a fifth embodiment of the present invention. Among FIG. 5AA to FIG. 5DD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1′ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2′ in the corresponding figures suffixed with A.

As illustrated in FIGS. 5AA to 5AD, a resist layer 50 is formed, in plan view, at a lower position in FIG. 5AA than the resist layer 13 in FIGS. 1GA to 1GD of the first embodiment so as to partly cover the Si pillars 4 a and 4 b. In the same manner as in the first embodiment, RIE is performed using, as masks, the resist layer 50 and the SiO₂ layers 11 a and 11 b formed on the side surfaces of the peripheries of the Si pillars 4 a and 4 b to form a WSi₂ layer 51 a containing B atoms, a WSi₂ layer 51 b containing As atoms, and a SiO₂ layer 52. The resist layer 50 is removed.

Next, as illustrated in FIGS. 5BA to 5BD, a SiO₂ layer 14 is formed on the SiO₂ layer 6 so as to have an upper surface that is flush with the upper surface of the SiO₂ layer 52. A HfO₂ layer 15, a TiN layer 16, and a SiO₂ layer (not illustrated) are entirely deposited. SiO₂ layers 52 a and 52 b are formed on the side surface of the TiN layer 16 that surrounds the Si pillars 4 a and 4 b by performing an etch-back process. A resist layer 53 that is connected to the Si pillars 4 a and 4 b in the upper part of FIG. 5BA so as to partly cover the Si pillars 4 a and 4 b in plan view is formed.

Next, as illustrated in FIGS. 5CA to 5CD, the TiN layer 16 is etched by RIE using, as masks, the resist layer 53 and the SiO₂ layers 52 a and 52 b formed on the side surfaces of the peripheries of the Si pillars 4 a and 4 b. Thus, a TiN layer 16 a is formed that is connected to the side surface of the HfO₂ layer 15 on the side surfaces of the Si pillars 4 a and 4 b and the surface of the HfO₂ layer 15 on the SiO₂ layer 14. The resist layer 53 is removed.

Next, as illustrated in FIGS. 5DA to 5DD, a SiO₂ layer 18, a P⁺ region 19 a, an N⁺ region 19 b, a HfO₂ layer 15 a, and a SiO₂ layer 21 are formed in the same manner as in the first embodiment. A contact hole 22 a is formed on the P⁺ region 19 a. A contact hole 22 b is formed on the N⁺ region 19 b. A contact hole 22 e is formed on the TiN layer 16 a. A contact hole 22 d is formed so as to be connected to the upper and side surfaces of the WSi₂ layers 51 a and 51 b. A power supply wiring metal layer VDD connected to the P⁺ region 19 a through the contact hole 22 a, a ground wiring metal layer VSS connected to the N⁺ region 19 b through the contact hole 22 b, an input wiring metal layer VIN connected to the TiN layer 16 a through the contact hole 22 e, and an output wiring metal layer VOUT connected to the WSi₂ layers 51 a and 51 b through the contact hole 22 d are formed on the SiO₂ layer 21. Thus, a CMOS inverter circuit is formed on the i layer substrate 1 a.

This embodiment provides the following advantages.

1. In the first embodiment, the majority of the WSi₂ layers 7 aa and 7 bb overlaps the TiN layer 16 a in plan view. On the other hand, in this embodiment, the WSi₂ layers 51 a and 51 b and the TiN layer 16 a do not overlap each other in plan view except for regions in which they surround the entire peripheries of the Si pillars 4 a and 4 b with an equal width. Thus, the capacitance between the gate TiN layer 16 a and the drain P⁺ region 12 a and N⁺ region 12 b can be reduced. This increases the speed of the CMOS inverter circuit.

2. It has been described in this embodiment that the WSi₂ layers 51 a and 51 b and the TiN layer 16 a are formed so as not to overlap each other in plan view except for regions in which the WSi₂ layers 51 a and 51 b and the TiN layer 16 a surround the entire peripheries of the Si pillars 4 a and 4 b with an equal width. However, even when the WSi₂ layers 51 a and 51 b and the TiN layer 16 a partly overlap each other in plan view in a region other than the regions in which they surround the entire peripheries of the Si pillars 4 a and 4 b with an equal width, the capacitance between the WSi₂ layers 51 a and 51 b and the TiN layer 16 a can be reduced. In terms of design, the overlap dimensions are determined in consideration of, for example, performance and cost.

3. The feature of this embodiment is that the overlapping of the WSi₂ layers 51 a and 51 b and the TiN layer 16 a is determined by both the rectangular pattern of the resist layer 50 used for forming the WSi₂ layers 51 a and 51 b and the rectangular pattern of the resist layer (not illustrated) for forming the TiN layer 16 a. The WSi₂ layers 51 a and 51 b and the TiN layer 16 a that surround the peripheries of the Si pillars 4 a and 4 b with an equal width are formed in a self-aligned manner with the SiO₂ layers 11 a, 11 b, 52 a, and 52 b. This indicates that the overlapping of the WSi₂ layers 51 a and 51 b and the TiN layer 16 a can be easily controlled. In addition to the overlapping, the shapes of the WSi₂ layers 51 a and 51 b and the TiN layer 16 a can also be easily controlled in consideration of, for example, performance and cost.

Sixth Embodiment

FIG. 6A to FIG. 6BE illustrate a method for producing a CMOS inverter circuit including an SGT according to a sixth embodiment of the present invention. Among FIG. 6AA to FIG. 6BD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1′ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2′ in the corresponding figures suffixed with A.

As illustrated in FIGS. 6AA to 6AD, Si pillars 4 a and 4B are formed on the i layer substrate 1 a. The Si pillar 4B is formed closer to the Si pillar 4 a than the Si pillar 4 b in the first embodiment. A SiO₂ layer 2 a and a SiN layer 3 a are formed on the Si pillar 4 a. A SiO₂ layer 2B and a SiN layer 3B are formed on the Si pillar 4B. A SiO₂ layer 6, a WSi₂ layer 7A containing B atoms, a WSi₂ layer 7B containing As atoms, and a SiO₂ layer 8 are formed on the peripheries of the Si pillars 4 a and 4B. By performing heat treatment, a P⁺ region 12 a is formed in a portion of the Si pillar 4 a that is in contact with the WSi₂ layer 7A, and an N⁺ region 12B is formed in a portion of the Si pillar 4B that is in contact with the WSi₂ layer 7B. A SiO₂ film (not illustrated) is entirely deposited by CVD and then etched back by RIE to form SiO₂ layers 55 on the side surfaces of the Si pillars 4 a and 4B. The SiO₂ layers 55 are formed so as to be connected to each other in a portion between the Si pillars 4 a and 4B.

Next, as illustrated in FIGS. 6BA to 6BD, the SiO₂ layer 8 and the WSi₂ layers 7A and 7B are etched using the SiO₂ layer 55 as a mask to form a SiO₂ layer 8A and WSi₂ layers 7Aa and 7Bb. Subsequently, the same processes as those in the first embodiment are performed to form a CMOS inverter circuit.

FIG. 6BE illustrates the relationship between the Si pillars 4 a and 4B, the P⁺ region 12 a, the N⁺ region 12B, and the WSi₂ layers 7Aa and 7Bb in plan view. The diagonally shaded area indicates the WSi₂ layers 7Aa and 7Bb. The WSi₂ layer 7Aa is constituted by a WSi₂ layer 57 a serving as a first alloy layer that is formed in a self-aligned manner with the P⁺ region 12 a so as to surround the entire periphery of the Si pillar 4 a, a WSi₂ layer 59 a serving as a second alloy layer that is partly in contact with the periphery of the WSi₂ layer 57 a in a connected manner, and a WSi₂ layer 58 a serving as a fourth alloy layer that partly surrounds the periphery of the WSi₂ layer 57 a and is connected to the WSi₂ layer 59 a (in the second embodiment, the CoSi₂ layers 24 a and 24 b serving as third alloy layers are formed in the surface layers of the Si pillars 4 a and 4 b). The WSi₂ layer 7Bb is constituted by a WSi₂ layer 57 b serving as a first alloy layer that is formed in a self-aligned manner with the N⁺ region 12B so as to surround the entire periphery of the Si pillar 4B, a WSi₂ layer 59 b serving as a second alloy layer that is partly in contact with the periphery of the WSi₂ layer 57 b in a connected manner, and a WSi₂ layer 58 b serving as a fourth alloy layer that partly surrounds the periphery of the WSi₂ layer 57 b and is connected to the WSi₂ layer 59 b.

In this embodiment, the WSi₂ layers 7Aa and 7Bb can be formed without using the resist layer 13 unlike in the first embodiment. This simplifies the process. Furthermore, the Si pillars 4 a and 4B are located close to each other and thus the density of the circuit is increased.

Seventh Embodiment

FIG. 7AA to FIG. 7CD illustrate a method for producing a CMOS inverter circuit including an SGT according to a seventh embodiment of the present invention. Among FIG. 7AA to FIG. 7CD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1′ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2′ in the corresponding figures suffixed with A.

As illustrated in FIGS. 7AA to 7AD, a P⁺ region 60 a and an N⁺ region 60 b are formed in a surface layer of an i layer substrate 1 by, for example, ion implantation. An i layer 1 b is formed on the P⁺ region 60 a and the N⁺ region 60 b by, for example, a Si epitaxial process. As in the first embodiment, a SiO₂ layer 2 a, a SiN layer 3 a, and a resist layer 5 a are formed on the i layer 1 b above the P⁺ region 60 a, and a SiO₂ layer 2 b, a SiN layer 3 b, and a resist layer 5 b are formed on the i layer 1 b above the N⁺ region 60 b.

Next, as illustrated in FIGS. 7BA to 7BD, the i layer 1 b, the P⁺ region 60 a, the N⁺ region 60 b, and the i layer substrate 1 are etched by RIE using, as masks, the SiO₂ layers 2 a and 2 b, the SiN layers 3 a and 3 b, and the resist layers 5 a and 5 b formed on the i layer 1 b. Thus, as in the first embodiment, a lower portion of the i layer substrate 1 is left as an i layer substrate 1 a and Si pillars 4 a and 4 b are formed on the i layer substrate 1 a. As a result, a P⁺ region 60 aa and an N⁺ region 60 bb are formed in lower portions of the Si pillars 4 a and 4 b. Then, a SiO₂ layer 6, a WSi₂ layer 61, and a SiO₂ layer 8 including a SiO₂ layer and a SiN layer from the bottom is formed on the i layer substrate 1 a on the peripheries of the Si pillars 4 a and 4 b.

Next, as illustrated in FIGS. 7CA to 7CD, the same processes as those in the first embodiment are performed. First, SiO₂ layers 11 a and 11 b are formed on the side surfaces of the peripheries of the Si pillars 4 a and 4 b. A resist layer 13 that partly covers the top portions of the Si pillars 4 a and 4 b in a connected manner is formed. The SiO₂ layer 8 and the WSi₂ layer 61 are etched by RIE using the SiO₂ layers 11 a and 11 b and the resist layer 13 as masks to form a SiO₂ layer 8 a and a WSi₂ layer 61 a.

Finally, the resist layer 13 is removed. Subsequently, by performing the same processes as those in the first embodiment, a CMOS inverter circuit is formed.

This embodiment provides the following advantages.

1. In this embodiment, before the formation of the WSi₂ layer 61, the P⁺ region 60 aa and the N⁺ region 60 bb are formed in the Si pillars 4 a and 4 b. Thus, the WSi₂ layer 61 a constituted by the first alloy layers that surround the entire peripheries of the P⁺ region 60 aa and the N⁺ region 60 bb and the second alloy layer that is partly in contact with the peripheries of the first alloy layers in a connected manner can be formed without forming the WSi₂ layer 7 a containing B atoms or the WSi₂ layer 7 b containing As atoms unlike in the first embodiment.

2. In the first embodiment, by performing heat treatment, donor or acceptor impurity atoms are forced toward the inside of the Si pillars 4 a and 4 b from the WSi₂ layer 7 a containing B atoms and the WSi₂ layer 7 b containing As atoms. Thus, the P⁺ region 12 a and the N⁺ region 12 b are formed. In this case, the heat treatment conditions such as temperature and time need to be set in consideration of, for example, separation of the WSi₂ layers 7 a and 7 b caused by generation of stress. In contrast, in this embodiment, such a problem does not arise because the P⁺ region 60 aa and the N⁺ region 60 bb are formed before the formation of the WSi₂ layer 61. Furthermore, the impurity concentration of the P⁺ region 60 aa and the N⁺ region 60 bb can be sufficiently increased. This can reduce the resistance of the drain P⁺ region 60 aa and N⁺ region 60 bb.

Herein, as in the first embodiment, a WSi₂ layer region containing B atoms (corresponding to the WSi₂ layer 7 a in the first embodiment) and a WSi₂ layer region containing As atoms (corresponding to the WSi₂ layer 7 b in the first embodiment) may be formed. In this case, the B atoms and the As atoms are forced toward the side surfaces of the peripheries of the P⁺ region 60 aa and the N⁺ region 60 bb from the WSi₂ layer regions. Thus, the P⁺ region 12 a and the N⁺ region 12 b are formed as in the first embodiment, which can further reduce the contact resistances between the P⁺ region 60 aa and the WSi₂ layer 61 a and between the N⁺ region 60 bb and the WSi₂ layer 61 a. Furthermore, even if the P⁺ region 12 a and the N⁺ region 12 b are formed to positions close to the centers of the P⁺ region 60 aa and the N⁺ region 60 bb and thus the P⁺ region 12 a and the N⁺ region 12 b overlap the P⁺ region 60 aa and the N⁺ region 60 bb, no problems arise because a high-concentration donor or acceptor impurity region is formed in the Si pillars 4 a and 4 b. The same applies to other embodiments according to the present invention.

Eighth Embodiment

FIGS. 8A to 8D illustrate a method for producing a CMOS inverter circuit including an SGT according to an eighth embodiment of the present invention. FIG. 8A is a plan view, FIG. 8B is a sectional view taken along line X-X′ in FIG. 8A, FIG. 8C is a sectional view taken along line Y1-Y1′ in FIG. 8A, and FIG. 8D is a sectional view taken along line Y2-Y2′ in FIG. 8A.

In the first embodiment, as illustrated in FIGS. 1GA to 1GD, the resist layer 13 is formed so as to partly cover the upper surfaces of the tops of the Si pillars 4 a and 4 b. On the other hand, in this embodiment, as illustrated in FIGS. 8A to 8D, a resist layer 13 a is formed by lithography so as to have an upper surface positioned lower than the upper surfaces of the tops of the Si pillars 4 a and 4 b. The resist layer 13 a is formed such that the upper surface of a resist layer (not illustrated) entirely applied is positioned lower than the upper surfaces of the tops of the Si pillars 4 a and 4 b by controlling, for example, the material for the resist layer, the viscosity, or the rotational speed during spin coating. The SiO₂ layer 8 (refer to FIGS. 1FA to 1FD) and the WSi₂ layers 7 a and 7 b (refer to FIGS. 1FA to 1FD) are etched by RIE using the resist layer 13 a, the SiN layers 3 a and 3 b, and the SiO₂ layers 11 a and 11 b as masks to form a SiO₂ layer 8 a and WSi₂ layers 7 aa and 7 bb as illustrated in FIGS. 1GA to 1GD. As in the first embodiment, the first alloy layers of the WSi₂ layers 7 aa and 7 bb that lie below the SiO₂ layers 11 a and 11 b are formed in a tubular shape with an equal width so as to surround the entire peripheries of the P⁺ region 12 a and the N⁺ region 12 b regardless of the mask misalignment in lithography during formation of the resist layer 13 a.

This embodiment provides the following advantage.

In the first embodiment, a resist film (not illustrated) is applied so as to have an upper surface positioned higher than the upper surfaces of the tops of the Si pillars 4 a and 4 b, and then the resist layer 13 is formed by lithography. In this case, a thick resist film is used and thus the forming precision of the resist layer 13 may deteriorate. In contrast, in this embodiment, a thin resist film is used and thus the resist layer 13 a is formed with high forming precision. In particular, this embodiment is effective for production of high-density SGT circuits.

Ninth Embodiment

FIG. 9AA to FIG. 9BD illustrate a method for producing a CMOS inverter circuit including an SGT according to a ninth embodiment of the present invention. This embodiment is provided to further enhance the features of the fourth embodiment. Among FIG. 9AA to FIG. 9BD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1′ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2′ in the corresponding figures suffixed with A.

As illustrated in FIGS. 9AA to 9AD, a SiN layer 45 is formed on the peripheries of the Si pillars 4 a and 4 b so as to have an upper surface positioned higher than the P⁺ region 42 a and the N⁺ region 42 b as in the case of FIGS. 4DA to 4DD. Holes that surround the side surfaces of the TiN layers 16 a and 16 b are formed in the side surfaces of the SiO₂ layers 38 a and 38 b such that the upper surface of the SiN layer 45 is flush with the lower ends of the holes. For example, a NiSi layer (not illustrated) is formed on the peripheries of the Si pillars 4 a and 4 b in plan view so as to be connected to the TiN layers 16 a and 16 b. A resist layer 13 b is formed on the NiSi layer by lithography so as to be partly connected to the peripheries of the SiO₂ layers 38 a and 38 b. The NiSi layer is etched using the resist layer 13 a and the SiO₂ layers 38 a and 38 b as masks to form a NiSi layer 46 a. The resist layer 13 b is removed.

Subsequently, by performing the same processes as those illustrated in FIGS. 4DA to 4DD, a CMOS inverter circuit is formed on the i layer substrate 1 a as illustrated in FIGS. 9BA to 9BD.

This embodiment provides the following advantages.

1. The SiO₂ layers 38 a and 38 b that surround the side surfaces of the gate TiN layers 16A and 16B function as material layers for forming contact holes used to connect the NiSi layer 46 a and the TiN layers 16A and 16B and also function as etching mask layers for forming the NiSi layer 46 a that surrounds the peripheries of the Si pillars 4 a and 4 b with an equal width. This allows formation of the NiSi layer 46 a that surrounds the peripheries of the Si pillars 4 a and 4 b with an equal width, and therefore a high-density circuit including SGTs can be produced without performing particular processes.

2. The NiSi layer 46 a is constituted by first conductor layers that are directly in contact with the side surfaces of the TiN layers 16A and 16B and surround the entire peripheries of the TiN layers 16A and 16B in a tubular shape with an equal width in plan view and a second conductor layer that is partly connected to the first conductor layers and extends in a horizontal direction. Since the first conductor layers are formed in a self-aligned manner with the SiO₂ layers 38A and 38B that surround the peripheries of the Si pillars 4 a and 4 b with an equal width, the first conductor layers can be formed regardless of the planar shape of the NiSi layer 46 a for forming the second conductor layer. Furthermore, in terms of design, the second conductor layer is not necessarily formed so as to surround the Si pillars 4 a and 4 b unlike in the fourth embodiment. This can increase the density of a circuit and improve the performance of the circuit compared with in the fourth embodiment.

Tenth Embodiment

FIG. 10AA to FIG. 10FD illustrate a method for producing a CMOS inverter circuit including an SGT according to a tenth embodiment of the present invention. Among FIG. 10AA to FIG. 10FD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1 ‘ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2’ in the corresponding figures suffixed with A.

In the process illustrated in FIGS. 1AA to 1AD, an i layer substrate 1 is disposed on a P layer substrate 70. In the same manner as in FIGS. 1AA to 1AD, the i layer substrate 1 is etched by, for example, RIE using the resist layers 5 a and 5 b, the SiN layers 3 a and 3 b, and the SiO₂ layers 2 a and 2 b as etching masks to form an i layer substrate 1 a and Si pillars 71 a and 71 b that lie on the i layer substrate 1 a. The resist layers 5 a and 5 b are removed. Thus, a structure illustrated in FIGS. 10AA to 10AD is obtained. The Si pillar 71 a is located below the SiO₂ layer 2 a and the SiN layer 3 a. The Si pillar 71 b is located below the SiO₂ layer 2 b and the SiN layer 3 b.

Next, as illustrated in FIGS. 10BA to 10BD, for example, SiO₂ layers 72 a and 72 b are formed so as to surround the side surfaces of the Si pillars 71 a and 71 b.

Next, as illustrated in FIGS. 10CA to 10CD, an N layer 73 is formed in a surface layer of the i layer substrate 1 a on the peripheries of the Si pillars 71 a and 71 b by performing ion implantation of phosphorus (P) using the SiO₂ layers 2 a, 2 b, 72 a, and 72 b and the SiN layers 3 a and 3 b as masks. Subsequently, a P⁺ region 74 is formed in a surface layer of the N layer 73 on the periphery of the Si pillar 71 a by performing lithography and ion implantation of B. Similarly, an N⁺ region 75 is formed in a surface layer of the N layer 73 on the periphery of the Si pillar 71 b by performing lithography and ion implantation of As. The P⁺ region 74 and the N⁺ region 75 are desirably separated from each other in plan view in consideration of diffusion of donor or acceptor impurity atoms in a width direction during heat treatment performed later.

Next, as illustrated in FIGS. 10DA to 10DD, heat treatment is performed to cause diffusion, thereby expanding the P⁺ region 74, the N⁺ region 75, and the N layer 73 in a length direction and a width direction. Thus, a P⁺ region 74 a, an N⁺ region 75 a, and an N layer 73 a are formed on the P layer substrate 70.

Next, as illustrated in FIGS. 10EA to 10ED, a resist layer 77 is formed between the Si pillars 71 a and 71 b so as to be in contact with the peripheries of the Si pillars 71 a and 71 b. Then, the P⁺ region 74 a, the N⁺ region 75 a, the N layer 73 a, and a surface layer of the P layer substrate 70 is etched using the resist layer 77, the SiO₂ layers 2 a, 2 b, 72 a, and 72 b, and the SiN layers 3 a and 3 b as masks. Thus, a P layer 70 b, an N layer 73 aa, and a P⁺ region 74 aa located in a bottom portion of the Si pillar 71 a and an N⁺ region 75 aa located in a bottom portion of the Si pillar 71 b are formed on the P layer 70 a from the bottom. Consequently, the Si pillars 71 a and 71 b are formed on a Si pillar base 76 that is constituted by the P layer 70 b, the N layer 73 aa, the P⁺ region 74 aa located in a bottom portion of the Si pillar 71 a, and the N⁺ region 75 aa located in a bottom portion of the Si pillar 71 b. The resist layer 77 is removed.

Thus, as illustrated in FIGS. 10FA to 10FD, in the Si pillar base 76, the P⁺ region 74 aa and the N⁺ region 75 aa are formed so as to surround the entire peripheries of the bottom portions of the Si pillars 71 a and 71 b in a tubular shape with an equal width in plan view. The P⁺ region 74 aa and the N⁺ region 75 aa are constituted by regions below the Si pillars 71 a and 71 b, tubular regions with an equal width, and a region that is partly connected to the tubular regions with an equal width and extends between the Si pillars 71 a and 71 b. Subsequently, by performing the same processes as those illustrated in FIG. 1HA to FIG. 1JD, a CMOS inverter circuit including SGTs on the Si pillar base 76 can be produced. The P⁺ region 74 aa and N⁺ region 75 aa are single crystal semiconductor layers containing donor or acceptor impurity regions and constitute the impurity regions and the wiring conductive layers.

In this embodiment, donor or acceptor impurity atoms are implanted into the P⁺ region 74 aa and the N⁺ region 75 aa in a high concentration to reduce the resistance of the P⁺ region 74 aa and the N⁺ region 75 aa. On the other hand, in the process illustrated in FIGS. 10DA to 10DD, a conductor layer such as a metal or alloy layer made of W, WSi, the like may be formed on the P⁺ region 74 a and the N⁺ region 75 a while the SiO₂ layers 72 a and 72 b are left. In the process illustrated in FIGS. 10EA to 10ED, a conductor layer such as a metal or alloy layer made of W, WSi, or the like may be formed on the exposed upper and side surfaces of the Si pillar base 76 while the SiO₂ layers 72 a and 72 b are left after removal of the resist layer 77. A conductor layer such as a metal or alloy layer made of W, WSi, or the like may also be formed in the whole region between the SiO2 layers 72 a and 72 b in plan view. This can generate a uniform electric field because of the PN junction of the P⁺ region 74 a and the N⁺ region 75 a in the bottom portions of the Si pillars 4 a and 4 b.

This embodiment provides the following advantage.

The SiO₂ layers 72 a and 72 b that surround the side surfaces of the Si pillars 71 a and 71 b are used as mask material layers for forming first conductive regions that surround the peripheries of the bottom portions of the Si pillars 71 a and 71 b in a tubular shape with an equal width as in the first embodiment. Furthermore, as illustrated in FIGS. 10CA to 10CD, the SiO₂ layers 72 a and 72 b function as mask material layers for forming the N layer 73, the P⁺ region 74, and the N⁺ region 75 in the ion implantation of donor or acceptor impurities. This can increase the density of a circuit and improve the performance of the circuit as in the first embodiment.

Eleventh Embodiment

FIG. 11AA to FIG. 11CD illustrate a method for producing a CMOS inverter circuit including an SGT according to an eleventh embodiment of the present invention. Among FIG. 11AA to FIG. 11CD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1′ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2′ in the corresponding figures suffixed with A.

In FIGS. 1HA to 1HD, instead of the TiN layer 16, a SiN/TiN layer 96 obtained by covering a TiN layer (not illustrated) with a thin SiN layer (not illustrated) is formed so as to surround the HfO₂ layer 15. As illustrated in FIGS. 11AA to 11AD, SiO₂ layers 52 a and 52 b and SiN layers 78 a and 78 b are formed around the Si pillars 4 a and 4 b so as to surround the side surface of the SiN/TiN layer 96. A resist layer 79 is formed so as to be partly in contact with the SiN layers 78 a and 78 b and extend between the Si pillars 4 a and 4 b in plan view.

Next, as illustrated in FIGS. 11BA to 11BD, the SiN/TiN layer 96 is etched using the resist layer 79 and the SiN layers 78 a and 78 b as masks. Thus, a SiN/TiN layer 96 a is formed that is constituted by regions on the side surfaces of the Si pillars 4 a and 4 b, regions that surround the peripheries of the Si pillars 4 a and 4 b in a tubular shape with an equal width, and a region that is partly in contact with the tubular regions and extends between the Si pillars 4 a and 4 b. The resist layer 79 is removed. The TiN layers at the end surfaces of the exposed SiN/TiN layer 96 a are oxidized to form TiNO layers 80 a and 80 b.

Next, the same processes as those illustrated in FIGS. 1IA to 11D and FIGS. 1JA to 1JD are performed. In this embodiment, as illustrated in FIGS. 11CA to 11CD, a contact hole 83 through which an input wiring metal layer Vin is connected is formed on the SiN/TiN layer 96 a between the Si pillars 4 a and 4 b so as to extend through the SiO₂ layers 21 and 18. A contact hole 84 through which an output wiring metal layer Vout is connected is formed on the WSi₂ layers 51 a and 51 b between the Si pillars 4 a and 4 b so as to extend through the SiO₂ layers 21 and 18, the HfO₂ layer 15, and the SiO₂ layer 8 a. Even when the contact hole 84 overlaps the SiN layers 78 a and 78 b that surround the Si pillars 4 a and 4 b in plan view, the SiN layers 78 a and 78 b serve as etching stop layers, which prevents a short-circuit between the output wiring metal layer Vout and the SiN/TiN layer 96 a. Thus, a CMOS inverter circuit including an SGT can be produced.

This embodiment provides the following advantages.

1. The SiN layers 78 a and 78 b that surround the side surfaces of the SiN/TiN layer 96 in a tubular shape with an equal width in plan view have both functions as etching masks for forming the SiN/TiN layer 96 a and etching stop layers for preventing a short-circuit between the output wiring metal layer Vout and the SiN/TiN layer 96 a through the contact hole 84. Thus, the distance between the contact hole 84 and the Si pillars 4 a and 4 b can be decreased in terms of design. This enables an increase in the density of a circuit including an SGT.

2. Similarly, in the formation of the contact hole 83 through which the input wiring metal layer Vin and the SiN/TiN layer 96 a are connected, the side surface of the SiN/TiN layer 96 a that surrounds the Si pillars 4 a and 4 b can be prevented from being etched when the contact hole 83 comes close to the Si pillars 4 a and 4 b in plan view because of mask misalignment in lithography. This enables an increase in the density of a circuit including an SGT.

Twelfth Embodiment

FIG. 12AA to FIG. 12DD illustrate a method for producing a CMOS inverter circuit including an SGT according to a twelfth embodiment of the present invention. Among FIG. 12AA to FIG. 12DD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1′ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2′ in the corresponding figures suffixed with A.

As illustrated in FIGS. 12AA to 12AD, for example, SiN layers 86 a and 86 b are formed instead of the SiO₂ layers 11 a and 11 b that surround the side surfaces of the Si pillars 4 a and 4 b with an equal width in FIGS. 1FA to 1FD.

Next, as illustrated in FIGS. 12BA to 12BD, a SiO₂ layer (not illustrated) is entirely deposited by CVD and then polished by CMP so as to have an upper surface that is flush with the upper surfaces of the SiN layers 3 a and 3 b. Thus, a SiO₂ layer 87 is formed. A resist layer 88 is formed by lithography so as to partly cover the Si pillars 4 a and 4 b in plan view and extend between the Si pillars 4 a and 4 b.

Next, as illustrated in FIGS. 12CA to 12CD, the SiO₂ layer (SiO₂ layer 8 in FIGS. 1EA to 1ED) is etched using the resist layer 88 and the SiN layers 86 a and 86 b as masks. Thus, WSi layers 7 aa and 7 bb and a SiO₂ layer 8 a are formed. The WSi layers 7 aa and 7 bb are constituted by regions that surround the peripheries of the Si pillars 4 a and 4 b in a tubular shape with an equal width so as to be in contact with the side surfaces of the Si pillars 4 a and 4 b and a region that is partly in contact with the tubular regions and extends between the Si pillars 4 a and 4 b. The resist layer 88 and the SiO₂ layer 83 a are removed.

Next, the SiN layers 86 a and 86 b illustrated in FIGS. 12DA to 12DD are removed. Then, by performing the same processes as those illustrated in FIG. 1HA to FIG. 1JD, a CMOS inverter circuit including an SGT can be formed on the i layer substrate 1 a.

This embodiment provides the following advantage.

In the first embodiment, the resist layer 13 having a thickness from the upper surface of the SiO₂ layer 8 to the tops of the Si pillars 4 a and 4 b needs to be patterned by lithography. It is difficult to pattern the thick resist layer 13 with high precision in the production of a high-density circuit. In contrast, in this embodiment, the SiO₂ layer 87 having an upper surface that is flush with the upper surfaces of the SiN layers 3 a and 3 b located in upper portions of the Si pillars 4 a and 4 b is formed, and the resist layer 88 is formed on a flat surface by lithography. Therefore, a high-density circuit is more easily produced in this embodiment than in the first embodiment.

Modification of Twelfth Embodiment

It has been described in the twelfth embodiment that a SiO₂ layer (not illustrated) is entirely deposited by CVD and then polished by CMP so as to have an upper surface that is flush with the upper surfaces of the SiN layers 3 a and 3 b, thereby forming a SiO₂ layer 87. This is performed in order to form the resist layer 88 on a flat surface by lithography. In the case where, for example, a SiO₂ layer or a C layer is formed by spin coating in which a flat upper surface is formed instead of the SiO₂ layer 87 formed by CVD, the upper surface of the SiO₂ layer or C layer is not necessarily flush with the upper surfaces of the SiN layers 3 a and 3 b located in upper portions of the Si pillars 4 a and 4 b and may be positioned higher than the tops of the Si pillars 4 a and 4 b. That is, this embodiment shows that a high-density circuit is easily produced by forming a resist layer on a flat material layer.

Thirteenth Embodiment

FIG. 13AA to FIG. 13BD illustrate a method for producing a CMOS inverter circuit including an SGT according to a thirteenth embodiment of the present invention. Among FIG. 13AA to FIG. 13BD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1 ‘ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2’ in the corresponding figures suffixed with A.

After the processes illustrated in FIG. 5AA to FIG. 5CD are performed, a W layer (not illustrated) is entirely deposited. A W layer (not illustrated) is formed by CMP so as to have a flat upper surface that is flush with the HfO₂ layer 15 positioned higher than the tops of the Si pillars 4 a and 4 b. As illustrated in FIGS. 13AA to 13AD, a resist layer 91 is formed on the HfO₂ layer 15 and the W layer (not illustrated) by lithography so as to partly overlap the Si pillars 4 a and 4 b in plan view. The W layer (not illustrated) and the TiN layer (TiN layer 16 in FIGS. 5BA to 5BD) are etched using, as masks, the resist layer 91, the SiO₂ layers 52 a and 52 b that surround the peripheries of the Si pillars 4 a and 4 b in a tubular shape with an equal width, the HfO₂ layer 15 on the Si pillars 4 a and 4 b, the SiN layers 3 a and 3 b, and the SiO₂ layers 2 a and 2 b. Thus, a W layer 90 and a TiN layer 16A are formed. The resist layer 91 is removed.

The same processes as those illustrated in FIGS. 5DA to 5DD are performed, except that instead of the contact hole 22 e, a contact hole 22E is formed on the W layer 90 on the TiN layer 16A as illustrated in FIGS. 13BA to 13BD. Thus, an input wiring metal layer VIN is electrically connected to the TiN layer 16A serving as a gate conductor layer through the contact hole 22E and the W layer 90 serving as a conductor. Consequently, a CMOS inverter circuit including SGTs can be formed on the i layer substrate 1 a. Instead of the W layer 90, a material layer that is constituted by a single layer or plural layers and is made of another metal or alloy or a low-resistance semiconductor containing a donor or acceptor impurity in a high concentration may be used.

This embodiment provides the following advantages.

1. In this embodiment, a W layer serving as a conductor is used instead of the SiO₂ layer 87 serving as an insulating layer in the twelfth embodiment. As in the twelfth embodiment, the resist layer 88 is formed on the HfO₂ layer 15 whose upper surface is flat and the W layer by lithography. Thus, as in the twelfth embodiment, a high-density circuit is also easily produced in this embodiment.

2. In the fifth embodiment, the contact hole 22 e is formed on the TiN layer 16 a as illustrated in FIGS. 5DA to 5DD. On the other hand, in this embodiment, the contact hole 22E is formed on the W layer 90 on the TiN layer 16A. Thus, the contact hole 22E can be formed so as to be shallower than the contact hole 22 e. Consequently, an SGT circuit is easily produced.

Fourteenth Embodiment

FIG. 14AA to FIG. 14DD illustrate a method for producing a CMOS inverter circuit including SGTs according to a fourteenth embodiment of the present invention. Among FIG. 14AA to FIG. 14DD, figures suffixed with A are plan views, figures suffixed with B are sectional views taken along line X-X′ in the corresponding figures suffixed with A, figures suffixed with C are sectional views taken along line Y1-Y1′ in the corresponding figures suffixed with A, and figures suffixed with D are sectional views taken along line Y2-Y2′ in the corresponding figures suffixed with A.

As illustrated in FIGS. 14AA to 14AD, AlO layers 3 aa and 3 bb are formed instead of the SiN layers 3 a and 3 b in FIGS. 1CA to 1CD, and a SiN layer 99 is formed instead of the SiO₂ layer 6 in FIGS. 1CA to 1CD. A SiO₂ layer 100 is formed on the SiN layer 99 and on the peripheries of the bottom portions of the Si pillars 4 a and 4 b by a flowable chemical vapor deposition (FCVD) method. A SiN layer (not illustrated) is entirely deposited. Polishing is performed such that the upper surface of the SiN layer is flush with the upper surfaces of the AlO layers 3 aa and 3 bb. Etching is performed by RIE until the upper surface of the smoothened SiN layer reaches the tops of the Si pillars 4 a and 4 b. An AlO layer (not illustrated) is entirely deposited. The AlO layer is etched by RIE such that AlO layers 101 a and 101 b are left on the side surfaces of the SiO₂ layers 2 a and 2 b and the AlO layers 3 aa and 3 bb. The SiN layer on the peripheries of the Si pillars 4 a and 4 b is etched by RIE using the AlO layers 3 aa, 3 bb, 101 a, and 101 b as masks to form SiN layers 102 a and 102 b that surround the side surfaces of the Si pillars 4 a and 4 b.

Next, as illustrated in FIGS. 14BA to 14BD, the SiO₂ layer 100 is etched by RIE using the AlO layers 3 aa, 3 bb, 101 a, and 101 b as masks to form SiO₂ layers 100 a and 100 b below the SiN layers 102 a and 102 b and on the side surfaces of the Si pillars 4 a and 4 b.

Subsequently, for example, after the Si pillar 4 b is covered with a resist layer by lithography, the SiO₂ layer 100 a is removed by etching. Then, the resist layer is removed. As illustrated in FIGS. 14CA to 14CD, a P⁺ region 103 a containing acceptor impurities is formed on the exposed side surface of the bottom portion of the Si pillar 4 a by a selective epitaxial crystal growth method, which is one of epitaxial crystal growth methods. A thin SiO₂ layer (not illustrated) is entirely deposited by ALD. After the Si pillar 4 b is covered with a resist layer, the thin SiO₂ layer that covers the entirety in advance and the SiO₂ layer 100 b are removed by etching. Then, the resist layer is removed. An N⁺ layer 103 b containing donor impurities is formed on the side surface of the bottom portion of the Si pillar 4 b by a selective epitaxial crystal growth method. A W layer 104 connected to the P⁺ region 103 a and the N⁺ region 103 b is formed.

Next, as illustrated in FIGS. 14DA to 14DD, a mask material layer 105 that is formed of a resist layer and partly overlaps the Si pillars 4 a and 4 b or the AlO layers 101 a and 101 b in plan view is formed. The W layer 104, the P⁺ region 103 a, and the N⁺ region 103 b are etched using the mask material layer 105, the AlO layers 3 a, 3 b, 101 a, and 101 b, and the SiN layers 102 a and 102 b as masks to form a W layer 104 a, a P⁺ region 103 aa, and an N⁺ region 103 bb that are present on the inner sides of the mask material layer 105 and the AlO layers 101 a and 101 b in plan view. Thus, a W layer 104 a connected to the P⁺ region 103 aa and the N⁺ region 103 bb is formed below the mask material layer and the P⁺ region 103 aa and the N⁺ region 103 bb that surround the Si pillars 4 a and 4 b with an equal width in plan view. By performing the processes illustrated in FIG. 1GA to FIG. 1JD, a CMOS inverter circuit including SGTs is formed. The P⁺ region 103 aa and N⁺ region 103 bb are single crystal semiconductor layers containing donor or acceptor impurity regions and constitute the impurity regions and the wiring conductive layers. After forming the P⁺ region 103 a and the N⁺ region 103 b, acceptor and donor impurity atoms diffuse into the Si pillars 4 a and 4 b by thermal processes. And the N⁺ region 103 aa and the P⁺ region 103 bb are formed in the side surface or the inside of the Si pillars 4 a and 4 b.

This embodiment provides the following advantages.

1. Since the P⁺ region 103 aa and the N⁺ region 103 bb are formed by a selective epitaxial crystal growth method, the P⁺ region 103 aa and the N⁺ region 103 bb are single-crystal layers. Therefore, the P⁺ region 103 aa and the N⁺ region 103 bb serve as a source and a drain of SGTs. For example, when the diameters of the Si pillars 4 a and 4 b decrease as the size of the circuit decreases, the increase in the electrical resistance of the P⁺ region 12 a and the N⁺ region 12 b formed inside the Si pillars 4 a and 4 b in FIGS. 1JA to 1JD can be prevented. In the heating process after the process in FIGS. 14DA to 14DD, a P⁺ layer and an N⁺ layer are formed on the side surfaces of or inside the Si pillars 4 a and 4 b that are in contact with the P⁺ region 103 aa and the N⁺ region 103 bb through thermal diffusion of acceptor or donor impurities, which does not impair a decrease in the resistance of the source and the drain. The same applies to the case where a P⁺ region and an N⁺ region are formed on the side surfaces of or inside the Si pillars 4 a and 4 b before formation of the P⁺ region 103 a and the N⁺ region 103 b. The same also applies to a P⁺ region and an N⁺ region formed on the tops of the Si pillars 4 a and 4 b.

2. In the description of this embodiment, the P⁺ region 103 aa and the N⁺ region 103 bb are formed by a selective epitaxial crystal growth method. Alternatively, the P⁺ region 103 aa and the N⁺ region 103 bb may be formed by, for example, alternately performing epitaxial crystal growth of Si and chemical dry etching (CDE) in a repeated manner. In the epitaxial crystal growth, a Si layer is deposited not only on the exposed portions of the Si pillars 4 a and 4 b, but also on the SiN layers 99, 102 a, and 101 b and the AlO layers 3 a, 3 b, 101 a, and 101 b serving as insulating layers. The Si layer deposited on the SiN layers 99, 102 a, and 101 b and the AlO layers 3 a, 3 b, 101 a, and 101 b is not a single-crystal layer, but an amorphous layer. The amorphous layer has a higher etching rate than the single-crystal layer. By intermittently performing CDE during epitaxial growth, a P⁺ region 103 a and an N⁺ region 103 b each formed of a single-crystal layer can be formed so as to be connected to the exposed side surfaces of the Si pillars 4 a and 4 b. Thus, a P⁺ region 103 a and an N⁺ region 103 b each formed of a single-crystal layer can be formed by an epitaxial crystal growth method different from the epitaxial crystal growth method described in FIGS. 14CA to 14CD.

3. In the first embodiment, as illustrated in FIGS. 1EA to 1ED, a SiO₂ film (not illustrated) is entirely deposited by CVD, and then the SiO₂ film is etched by RIE so as to remain on the side surfaces of the Si pillars 4 a and 4 b. Thus, the SiO₂ layers 11 a and 11 b are formed on the side surfaces of the Si pillars 4 a and 4 b. In this case, the thickness of the SiO₂ layers 11 a and 11 b decreases in the upper part and increases in the lower part. Since the SiO₂ layers 11 a and 11 b are etched in plan view during the RIE of the SiO₂ layer 8 and the WSi₂ layers 7 a and 7 b at a low etching rate, the decrease in the width of the bottom portions of the SiO₂ layers 11 a and 11 b in plan view cannot be avoided. This causes a variation in the width of the WSi₂ layers 7 aa and 7 bb in plan view. As a result, the mask alignment tolerance in the mask design needs to be increased, which makes it difficult to increase the density of the circuit. On the other hand, in this embodiment, the AlO layers 101 a and 101 b having an equal width in plan view are first formed on the peripheries of the AlO layers 3 aa and 3 bb and the SiO₂ layers 2 a and 2 b. The SiN layer (not illustrated) formed on the outer sides of the Si pillars 4 a and 4 b is etched by RIE using the AlO layers 101 a and 101 b as masks to form the SiN layers 102 a and 102 b having an equal width in plan view on the side surfaces of the Si pillars 4 a and 4 b. The heights of the AlO layers 101 a and 101 b are sufficiently smaller than those of the Si pillars 4 a and 4 b, and thus AlO layers 101 a and 101 b having a small variation in width in plan view are formed. Since the SiN layer is etched using the AlO layers 101 a and 101 b as masks, SiN layers 102 a and 102 b having a small variation in width in plan view are formed. This increases the density of the circuit.

4. In this embodiment, the P⁺ region 103 a and the N⁺ region 103 b are formed so as to be present outward with respect to the peripheral lines of the SiN layers 102 a and 102 b in plan view. In this case, the P⁺ region 103 a and the N⁺ region 103 b that are not in contact with the low-resistance W layer 104 a in plan view are formed on the peripheries of the Si pillars 4 a and 4 b. This increases the PN junction resistance. Alternatively, the P⁺ region 103 a and the N⁺ region 103 b may be formed so as to be present inward with respect to the peripheral lines of the SiN layers 102 a and 102 b in plan view, and then a W layer may be formed on the side surfaces of the P⁺ region 103 a and the N⁺ region 103 b by a selective growth method. Thus, the P⁺ region 103 aa and the N⁺ region 103 bb are formed such that the entire peripheries of the P⁺ region 103 aa and the N⁺ region 103 bb are in contact with the W layer 104 a in plan view. This decreases the PN junction resistance of the P⁺ region 103 aa and the N⁺ region 103 bb.

In each of the above embodiments, a Si pillar made of silicon is used. However, the technical idea of the present invention is applicable to SGTs partly or wholly formed of a semiconductor material other than silicon.

In the first embodiment, the TiN layer 16 a is used as a gate conductive layer. However, the gate conductive layer may be a different metal layer or a conductor material layer. The gate conductor layer may be a multilayer conductor layer. The same applies to other embodiments according to the present invention.

In the first embodiment, the SiO₂ layers 11 a and 11 b that surround the Si pillars 4 a and 4 b are used. However, any other material layer functioning as an etching mask may be used for the etching of the WSi₂ layers 7 a and 7 b. The material layer may be constituted by a single layer or plural layers. The same applies to other embodiments according to the present invention.

In the first embodiment, the SiO₂ layers 11 a and 11 b that surround the Si pillars 4 a and 4 b are used as etching masks for the WSi₂ layers 7 a and 7 b. The SiO₂ layers 11 a and 11 b are formed by entirely depositing a SiO₂ film (not illustrated) by CVD and etching the SiO₂ film by RIE such that portions of the SiO₂ film are left on the side surfaces of the Si pillars 4 a and 4 b. In this case, as illustrated in FIGS. 1FA to 1FD, the sections of the SiO₂ layers 11 a and 11 b are small in the upper portions and large in the bottom portions. In this case, the side surfaces of the upper portions of the Si pillars 4 a and 4 b also need to be covered with the SiO₂ layers 11 a and 11 b. On the other hand, for example, a SiO₂ layer is formed so as to cover the Si pillars 4 a and 4 b, the SiO₂ layers 2 a and 2 b, and the SiN layers 3 a and 3 b. Then, the SiO₂ layer is polished by CMP so as to have an upper surface that is flush with the upper surfaces of the SiN layers 3 a and 3 b. Subsequently, the SiN layers 3 a and 3 b are etched back so as to have an upper surface positioned higher than the tops of the Si pillars 4 a and 4 b. A mask SiN layer for the SiO₂ layers 11 a and 11 b is formed on the side surfaces of the peripheries of the SiO₂ layers 2 a and 2 b and the SiN layers 3 a and 3 b. The SiO₂ layer is etched using the mask SiN layer as a mask to form a mask SiO₂ layer. Thus, a mask SiO₂ layer for the SiO₂ layers 11 a and 11 b is formed on the side surfaces of the Si pillars 4 a and 4 b with an equal thickness in the vertical direction. Thus, the WSi₂ layers 7 a and 7 b are etched with certainty. The same (including the formation of the gate TiN layer 16 a in the thirteenth embodiment) applies to other embodiments according to the present invention.

In the first embodiment, the resist layer 13 constituted by a single layer is used as a mask material layer. Instead of the resist layer 13, a single inorganic material layer or a single organic material layer, a plurality of inorganic material layers, a plurality of organic material layers, or a plurality of material layers including at least one inorganic material layer and at least one organic material layer may be used. For example, a material layer patterned by lithography is disposed in an upper part, and one or more inorganic material layers or organic material layers disposed below the patterned material layer are etched using the patterned material layer as a mask. The WSi₂ layers 7 a and 7 b may be etched by partly or wholly using the one or more inorganic material layers or organic material layers as masks. The same applies to other embodiments according to the present invention.

In the first embodiment, the SiO₂ layer 6, the WSi₂ layer 7, and the SiO₂ layer 8 are formed by sputter deposition, but they may be formed by entirely depositing material layers by, for example, CVD and then etching back the material layers. Alternatively, another method may be employed in which any of the SiO₂ layer 6, the WSi₂ layer 7, and the SiO₂ layer 8 is formed by an etch-back process and the other is formed by a sputtering process. The same applies to other embodiments according to the present invention.

In the first embodiment, as illustrated in FIGS. 1AA to 1AD, the SiN layers 3 a and 3 b are formed below the resist layers 5 a and 5 b. However, for example, a two-layer structure including SiO₂ and SiN from above may be employed. Alternatively, another material layer constituted by a single layer or plural layers may be used, or such material layers may be combined with each other. The same applies to the SiO₂ layers 2 a and 2 b. The same applies to other embodiments according to the present invention.

In the first embodiment, before the SiO₂ layers 11 a and 11 b are formed on the side surfaces of the Si pillars 4 a and 4 b, ion implantation of As and B into the WSi₂ layer 7 is performed to form the WSi₂ layers 7 a and 7 b containing As and B. However, the ion implantation of As and B may be performed after the SiO₂ layers 11 a and 11 b are formed. By the heat treatment performed later, the WSi₂ layers 7 a and 7 b containing As and B can be formed to the side surfaces of the Si pillars 4 a and 4 b through thermal diffusion of As and B. Alternatively, the WSi₂ layers 7 a and 7 b containing a donor or acceptor impurity may be formed by applying a gas containing donor or acceptor impurity atoms from the outside or through thermal diffusion from an impurity layer. In this case, a diffusion mask material layer needs be formed on each of the WSi₂ layers 7 a and 7 b. The same applies to other embodiments according to the present invention.

In each of the above embodiments, the case where the Si pillars 4 a, 4 b, and 4B have a circular shape in plan view has been described. However, it is obvious that the Si pillars 4 a, 4 b, and 4B may have an elliptical shape.

In each of the above embodiments, the case where the side surfaces of the Si pillars 4 a, 4 b, and 4B have a columnar shape that is vertical to the plane of the i layer substrate has been described. However, the side surfaces of the Si pillars 4 a, 4 b, and 4B may have a trapezoidal shape or a barrel-like shape as long as the structure in each embodiment is realized.

The WSi₂ layer is used in the first embodiment, the CoSi₂ layer is used in the second embodiment, and conductive material layers such as the P⁺ region 74 aa and N⁺ region 75 aa serving as semiconductor layers containing a donor or acceptor impurity are used in the tenth embodiment. However, another material layer formed of, for example, a metal, a semiconductor, or an alloy may be used in each embodiment as long as the structure in each embodiment is realized. The same applies to other embodiments according to the present invention.

In the first embodiment, the P⁺ region 12 a and the N⁺ region 12 b are formed on the peripheries of the Si pillars 4 a and 4 b. In the fourth embodiment, the P⁺ region 42 a and the N⁺ region 42 b are formed so as to extend to the centers of the Si pillars 4 a and 4 b. In both the embodiments, the depth of such a P⁺ region and an N⁺ region formed in the Si pillars 4 a and 4 b varies depending on the width of the Si pillars 4 a and 4 b and the process temperature. As a result, such a P⁺ region and an N⁺ region may be formed to the peripheries of the Si pillars 4 a and 4 b or to the centers of the Si pillars 4 a and 4 b. The same applies to other embodiments according to the present invention.

In the descriptions of the second embodiment and the fourth embodiment, the CoSi₂ layers 24 a, 24 b, 43 a, and 43 b serving as silicide layers are formed on the peripheries of the Si pillars 4 a and 4 b. The formation of the silicide layers to the centers of the Si pillars 4 a and 4 b does not depart from the scope of the present invention at all. The same applies to other embodiments according to the present invention.

In the first embodiment, the description has been made using the WSi₂ layers 7 aa and 7 bb as wiring alloy layers. In this case, almost no silicide layer is formed in the Si pillars 4 a and 4 b. However, when the interface between the WSi₂ layers 7 aa and 7 bb and the Si pillars 4 a and 4 b is observed under magnification, a thin silicide layer is formed in the Si pillars depending on the heat treatment conditions in the processes.

In the first embodiment, a well layer is not formed in lower portions of the Si pillars 4 a and 4 b below the P⁺ region 12 a and the N⁺ region 12 b. However, after the formation of the Si pillars 4 a and 4 b, a well layer may be formed by using, for example, ion implantation, solid-state diffusion, or an epitaxial layer. This does not depart from the scope of the present invention at all. The same applies to other embodiments according to the present invention.

In the fourth embodiment, the TiN layers 16A and 16B and the NiSi layer 46 serving as a wiring conductor layer are connected to each other at the intermediate positions of the TiN layers 16A and 16B in the vertical direction. This reduces the capacitance between the gate TiN layers 16A and 16B and the source P⁺ region 42 a and N⁺ region 42 b. The same applies to other embodiments according to the present invention.

In the fifth embodiment, the WSi₂ layers 51 a and 51 b that extend between the two Si pillars 4 a and 4 b are formed so as not to overlap the TiN layer 16 a in plan view. Even when this embodiment is applied to formation of a circuit including one Si pillar or three or more Si pillars, the capacitance can be reduced in the same manner.

In the fifth embodiment, the WSi₂ layers 51 a and 51 b and the TiN layer 16 a are formed such that the WSi₂ layers 51 a and 51 b and a portion of the TiN layer 16 a that extends in a horizontal direction do not overlap each other in plan view. This reduces the capacitance between the WSi₂ layers 51 a and 51 b and the TiN layer 16 a. The same applies to other embodiments according to the present invention.

It has been described in the fifth embodiment that the overlapping of the WSi₂ layers 51 a and 51 b and the TiN layer 16 a can be easily controlled by changing the rectangular pattern of the resist layer 50 used for forming the WSi₂ layers 51 a and 51 b and the rectangular pattern of the resist layer (not illustrated) used for forming the TiN layer 16 a. This is applicable to, for example, not only reduction in the capacitance between the WSi₂ layers 51 a and 51 b and the TiN layer 16 a, but also reduction in the capacitance between other wiring layers. The same applies to other embodiments according to the present invention.

In the eleventh embodiment, the SiO₂ layers 52 a and 52 b and the SiN layers 78 a and 78 b are formed so as to surround the Si pillars 4 a and 4 b in a tubular shape with an equal width. In this case, the SiN layers 78 a and 78 b serve as etching stoppers when the contact holes 83 and 84 that extend through the SiO₂ layers 18 and 21 are formed. Any other material layer that serves as an etching stopper may be used instead of the SiN layers 78 a and 78 b. The eleventh embodiment is applicable to other embodiments according to the present invention.

In the eleventh embodiment, the TiN layers at the end surfaces of the exposed SiN/TiN layers 96 a are oxidized to form the TiNO layers 80 a and 80 b, so that a short-circuit between the output wiring metal layer Vout and the SiN/TiN layer 96 a is prevented. However, instead of the TiNO layers 80 a and 80 b, another material layer such as a SiO₂ layer formed by a fluid process may be embedded. Alternatively, the short-circuit between the output wiring metal layer Vout and the SiN/TiN layer 96 a may be prevented by another method. The same applies to other embodiments according to the present invention.

It has been described in the twelfth embodiment that by forming the resist layer 88 on a flat material layer (the SiO₂ layer 87 and the SiN layers 3 a and 3 b in FIGS. 12BA to 12BD) having an upper surface positioned higher than the tops of the Si pillars 4 a and 4 b, a high-density circuit is easily produced compared with in the first embodiment. The same applies to other embodiments according to the present invention.

The resist layer 88 and the SiO₂ layer 83 a in the twelfth embodiment may each be another material layer constituted by a single layer or plural layers.

The twelfth embodiment is an embodiment in which the present invention is applied to the formation of the WSi₂ layers 7 aa and 7 bb connected to the P⁺ region 12 a and the N⁺ region 12 b. This embodiment is also applicable to the formation of the TiN layer 16 a serving as a gate conductor layer in the fifth embodiment. The same applies to other embodiments according to the present invention.

In the twelfth embodiment, the SiO₂ layer 87 is formed on the peripheries of the Si pillars 4 a and 4 b. However, another material layer constituted by a single layer or plural layers may be used instead of the SiO₂ layer 87. The same applies to other embodiments according to the present invention.

In the thirteenth embodiment, the TiN layer 16 a is formed using the SiO₂ layers 2 a and 2 b as masks. In this case, another material layer such as a conductor material layer may be used instead of the SiO₂ layers 2 a and 2 b as long as the other material layer serves as a mask for TiN etching. When a conductor material layer is employed, the contact resistance between the TiN layer 16 a and the W layer 90 can be reduced. The same applies to other embodiments according to the present invention.

In the thirteenth embodiment, the contact hole 22E is formed on the W layer 90. However, the contact hole 22E may be formed so as to be in contact with the side surface of the W layer 90 as long as the W layer 90 and the input wiring metal layer VIN are connected to each other.

The P⁺ region 103 aa and the N⁺ region 103 bb formed by a selective epitaxial crystal growth method in the fourteenth embodiment may be formed of another semiconductor material such as Si or SiGe.

The W layers 104 and 104 a in the fourteenth embodiment may be formed using another conductor layer including one or more layers.

In each of the above embodiments, a SOI (silicon on insulator) substrate including an insulating substrate may also be used instead of the i layer substrate 1 a.

In each of the above embodiments, the HfO₂ layers 15, 15 a, 15A, 15B, and 36 are used as gate insulating layers. However, the material for the gate insulating layers is not limited to HfO₂, and another insulating layer constituted by a single layer or plural layers may be used.

In the first embodiment, the case where a single SGT is formed in each of the Si pillars 4 a and 4 b has been described. However, since the present invention relates to the P⁺ region 12 a and the N⁺ region 12 b formed in the bottom portions of the Si pillars 4 a and 4 b and to the WSi₂ layers 7 aa and 7 bb serving as wiring alloy layers connected to the P⁺ region 12 a and the N⁺ region 12 b, the present invention is applicable to formation of a circuit including a plurality of SGTs in a single semiconductor pillar. The same applies to other embodiments according to the present invention.

In the first embodiment, the description has been made using the case where the source and drain located in the upper and lower portions of SGTs are constituted by the same P⁺ regions 12 a and 19 a or the same N⁺ regions 12 b and 19 b. However, the first embodiment is also applicable to a tunneling SGT in which the source and drain of one or both of SGTs are formed of impurity layers having different conductivity types. The same applies to other embodiments according to the present invention.

The SGT has a structure in which a gate insulating layer is formed on a periphery of a semiconductor pillar and a gate conductor layer is formed on a periphery of the gate insulating layer. A flash memory device including a conductor layer electrically floating between the gate conductor layer and the gate insulating layer is also one embodiment of the SGT, and the technical idea of the present invention can be applied to such a flash memory device.

In each of the above embodiments, the case where only an SGT is formed in the semiconductor pillar has been described. However, the technical idea of the present invention is applicable to a method for producing a semiconductor device including an SGT and an element (e.g., a photodiode) other than the SGT incorporated therein.

In the first embodiment, the P⁺ region 12 a, the N⁺ region 12 b, and the WSi₂ layers 7Aa and 7Ba are formed so as to surround the semiconductor pillars in a tubular shape with an equal width in plan view, but these structures are not limited thereto. The sectional outer shapes of these structures in plan view may be dependent on the sectional shape of the semiconductor pillar, that is, may be shapes similar to the sectional shape of the semiconductor pillar. For example, when the sectional shape of the semiconductor pillar is a square, the sectional outer shape of such a structure may be a square or a rectangle. When the sectional shape of the semiconductor pillar is an ellipse, the sectional outer shape of such a structure may be an ellipse, a circle, or an oval. The sectional shape of such a structure may be any shape that surrounds the semiconductor pillar in plan view. In the case where such a sectional shape is shared, by using, as an etching mask, a material layer that surrounds the semiconductor pillar and has the sectional shape, the P⁺ region 12 a and the WSi₂ layer 7Aa and/or the N⁺ region 12 b and the WSi₂ layer 7Ba that are arranged in a direction vertical to the substrate can be formed in a self-aligned manner so as to have the same sectional shape. The same applies to other embodiments according to the present invention.

Various embodiments and modifications of the present invention can be made without departing from the broad spirit and scope of the present invention. The above-described embodiments are illustrative examples of the present invention and do not limit the scope of the present invention. The above-described embodiments and modifications can be freely combined with each other. Furthermore, embodiments from which some of constituent features of the embodiments are removed as required are also within the technical idea of the present invention.

The method for producing a pillar-shaped semiconductor device according to the present invention is useful for providing high-density, high-performance semiconductor devices including SGTs. 

1. A method for producing a pillar-shaped semiconductor device, the method comprising: a step of providing a structure including: a substrate, a first semiconductor pillar that stands on a plane of the substrate in a vertical direction, and a first impurity region that is in contact with a lower portion of the first semiconductor pillar or a side surface of the lower portion and contains a donor or acceptor impurity atom; a step of forming a first material layer that has conductivity, extends in a horizontal direction, and is connected to, in plan view, at least one of an entire periphery of the lower portion of the first semiconductor pillar and an entire periphery of a first conductor layer surrounding a first insulating layer surrounding the first semiconductor pillar; a step of forming, on the first material layer, a second material layer that surrounds the first semiconductor pillar in plan view; a step of forming, on the first material layer, a third material layer that is partly connected to the second material layer in plan view; and a step of etching the first material layer using the second material layer and the third material layer as masks, wherein a first region of the first material layer that surrounds the first semiconductor pillar in plan view is formed below the second material layer, and a second region of the first material layer that is partly connected to the first region in plan view is formed below the third material layer.
 2. The method for producing a pillar-shaped semiconductor device according to claim 1, wherein the second material layer is formed so as to surround the first semiconductor pillar in a tubular shape with an equal width.
 3. The method for producing a pillar-shaped semiconductor device according to claim 1, wherein the first material layer contains a semiconductor atom, a metal atom, and the donor or acceptor impurity atom.
 4. The method for producing a pillar-shaped semiconductor device according to claim 1, wherein the first material layer is formed of a semiconductor layer containing the donor or acceptor impurity atom or a metal layer.
 5. The method for producing a pillar-shaped semiconductor device according to claim 1, wherein the step of providing a structure includes a step of forming the first impurity region by performing heat treatment to force the donor or acceptor impurity atom toward an inside of the first semiconductor pillar from the first material layer containing the donor or acceptor impurity atom.
 6. The method for producing a pillar-shaped semiconductor device according to claim 1, the method comprising: a step of forming the first impurity region before formation of the first semiconductor pillar.
 7. The method for producing a pillar-shaped semiconductor device according to claim 1, wherein the second material layer is formed of at least the first insulating layer and the first conductor layer.
 8. The method for producing a pillar-shaped semiconductor device according to claim 1, wherein the second material layer is formed of a second insulating layer that surrounds an entire periphery of the first conductor layer, and the first material layer is connected to an entire periphery of the first conductor layer in plan view.
 9. The method for producing a pillar-shaped semiconductor device according to claim 1, wherein the first region of the first material layer includes a third region that is connected to the first impurity region and surrounds the first semiconductor pillar and a fourth region that surrounds an entire periphery of the first conductor layer so as to be in contact with the entire periphery of the first conductor layer, the second region of the first material layer includes a fifth region that is partly connected to the third region and extends in the horizontal direction and a sixth region that is partly connected to the fourth region and extends in the horizontal direction, and the fifth region and the sixth region are formed so as to be away from each other or to partly overlap each other in plan view.
 10. The method for producing a pillar-shaped semiconductor device according to claim 1, the method comprising: a step of entirely forming a third insulating layer after the structure is provided; and a step of forming a first contact hole that extends through the third insulating layer, wherein at least a surface layer of the second material layer serves as an etching stopper for an etchant used for forming the first contact hole.
 11. The method for producing a pillar-shaped semiconductor device according to claim 1, wherein an upper surface of the third material layer is positioned lower than a top of the first semiconductor pillar in the vertical direction.
 12. The method for producing a pillar-shaped semiconductor device according to claim 1, the method comprising: a step of forming a fourth material layer on the first material layer on a periphery of the first semiconductor pillar, the fourth material layer having a flat upper surface that is flush with or is positioned higher than an upper surface of a top of the first semiconductor pillar; a step of forming, on the fourth material layer, a fifth material layer that partly overlaps the first region in plan view; and a step of forming a sixth material layer by etching the fourth material layer using the fifth material layer as a mask, wherein the third material layer is formed by performing etching using both the fifth material layer and the sixth material layer as masks or the sixth material layer as a mask.
 13. The method for producing a pillar-shaped semiconductor device according to claim 12, the method comprising: a step of etching the fourth material layer having conductivity such that the fourth material layer has an upper surface positioned lower than the top of the first semiconductor pillar; and a step of forming a second contact hole such that the second contact hole is in contact with the sixth material layer.
 14. The method for producing a pillar-shaped semiconductor device according to claim 1, the method comprising: a step of forming a second semiconductor pillar that is adjacent to the first semiconductor pillar; a step of forming, on the first material layer, a seventh material layer that surrounds the second semiconductor pillar in plan view; a step of forming the third material layer that is partly connected to each of the second material layer and the seventh material layer in plan view; and a step of etching the first material layer using the second material layer, the third material layer, and the seventh material layer as masks, wherein the first region of the first material layer that surrounds the first semiconductor pillar in plan view is formed below the second material layer, a seventh region of the first material layer that surrounds the second semiconductor pillar in plan view is formed below the seventh material layer, and the second region of the first material layer that is partly connected to each of the first region and the seventh region in plan view is formed below the third material layer.
 15. The method for producing a pillar-shaped semiconductor device according to claim 14, wherein the second material layer and the seventh material layer are formed in a connected manner between the first semiconductor pillar and the second semiconductor pillar in plan view, the method further comprising a step of etching the first material layer using the second material layer and the seventh material layer as masks.
 16. The method for producing a pillar-shaped semiconductor device according to claim 1, wherein a part contacted with the side surface of the first semiconductor pillar or entirety of the first material layer is formed with a single crystal semiconductor layer containing donor or acceptor impurity atoms.
 17. The method for producing a pillar-shaped semiconductor device according to claim 16, wherein the single crystal semiconductor layer is formed as the first impurity region.
 18. The method for producing a pillar-shaped semiconductor device according to claim 1, wherein a part or entirety of the first impurity region is formed on the side surface of the lower portion of the first semiconductor pillar by an epitaxial crystal growth method.
 19. The method for producing a pillar-shaped semiconductor device according to claim 18, wherein a part or entirety of the first impurity region is formed on the side surface of the lower portion of the first semiconductor pillar by a selective epitaxial crystal growth method.
 20. The method for producing a pillar-shaped semiconductor device according to claim 18, the method comprising: a step of partly etching the first impurity region using the second material layer as a mask in plan view.
 21. The method for producing a pillar-shaped semiconductor device according to claim 18, the method comprising: a step of forming the first impurity region by the epitaxial crystal growth method such that a periphery of the first impurity region in plan view is present inward with respect to a periphery of the second material layer; a step of forming a fourth material layer that has conductivity and is in contact with a side surface of the first impurity region; and a step of etching the fourth material layer using the second material layer as a mask. 